Specification / Schematics

[mrgs]

[off]On the last weekend I vectorized the PNG image of the available Parallella Board rev3. Attached please find an exported 'bitmap' about it. Please NOTE THIS IS JUST FOR FUN(!)[/off] Some question have arise:
- SDIO at SD? - (!) FIXME -
- Zynq boot source selection? (What about the device mode pins?)
- 3-pin 'Berg' connector for what? : RESET / UART / BOOT CONFIG / MEASUREMENT / ...
- Figure 2 : 800 MHz (XC7Z020-3CLG400C) (!) FIXME : '-3' and 'C' (speed grade and temperature range).
- SDIO_1 : MIO[15:10]? Figure 1.

Additional typos in the "Parallella Reference Manual 4.12.2.13" at the attached file. Regards, Gabor

[trioflex]

[mrgs]

Hi Antti, thank You for Your comment. Well, (a) I 'imagined' a 'combo SD/SDIO' card, (b) I guess, the '1 bit' mode at the current design just a 'temporary state' should be 'fixable'. (I have marked like a typo) (c) boot mode: Well, a configurable boot source could be better, but the current state is acceptable wide range of developers. (Who like to hack SPI flash, he/she has JTAG way) Additionally: during the 'OS developing/tuning' You can use LAN for OS boot. (SD is not so practical in this case). (d) header and reset button : Please note, the position of the button/LEDs just guessing. Have a nice day! Regards, Gabor

[mrgs]

[off]Attached please find the vector graphics (in SVG) 'design copy' about the Parallella Board rev3 'just for fun'[on]. Well, it could be useful?!, if You like to ['measure' | pick up | drawing, write on | ...] it ... Have fun(!) Regards, Gabor