IO connectors on Parallella rev0

[trioflex]

[Veqtor]

Yeah well the PEC power and PEC FPGA connectors are the most important then and we need a way to access them, if they don't need ultra fast IO then perhaps they are better substituted for standard header rows! If they are highly inaccesible to the average user then I can see a lot of complaining about the lack of hack-and-expandability.

I think a lot of people bought a parallela board thinking it would be a very hackable linux-arduino-supercomputer, but these headers might seriously put off a lot of people from buying them after the kickstarter backers get their boards.

At least some day 1 breakout needs to be supplied, ideally to the kickstarter backers too, since I believed I would be able to access the FPGA pins without getting a breakout board manufactured industrially (those headers don't seem to be solderable by hand and even if they were, the small pin spacing makes it very hard to etch boards in your kitchen, not to mention sourcing connectors in small quantities).

So yes, I find this choice of connectors quite concerning, can we put another breakout for the FPGA and power pins?

Another thing: Are we sure the epiphany chip connects to the zynq in a way that doesn't obstruct any of the 17 AMS ADC's? That is, are they brought out to the FPGA header? For my application they are invaluable!

[tnt]

[tnt]

[Sanjuro]

Is there any information about vertical placement of I/O connectors? In parallella_reference I see only horizontal dimensions.

[Dr.BeauWebber]

Hi,
Avnet appear to have accepted an order from me to ship in 12 connectors from the USA, backordered with 1 week lead time, with most of the charge freight and duty.
Supplier P/N: BTH-030-01-F-D-A
Samtec Inc.
Conn Micro Terminal HDR 60 POS 0.5mm Solder ST SMD Tube

I aim to interface these to my credit-card sized instrumentation boards.
I will build an interface card with the PEC connectors on one side and 2x 64 way (dual row x 32) connectors with 0.1" spacing, to act as break-out or for my instrumentation boards. As people have said, we still need the Y-layout spacing, before we can lay out anything.

If you have an interest in these interface boards, or just the PEC connectors, please let me know and I will see what I can do.
Cheers,
Dr. Beau Webber

[Gravis]

[user99]

Will the Z-7010 version have have the same connectivity as the 7020 version in regards to the FPGA GPIO pins?
In the reference pdf, page 16 shows the differences between the 7010 and 7020 boards, there is "Bank-13 IO Pins No " for the 7010.

[LamsonNguyen]

The basic 7010 board comes without GPIO, though it can be added on.

[tnt]

The 7010 doesn't have a bank13 so it only has about half the GPIO of the 7020 one. The others are NC.