update: I thought this project was basically it but I wanted to give a shot to the Xilinx FIR_compiler IP, thus having the crossovers done in the PL instead of IIR filters implemented in the PS.
I'm pretty pleased with the results, it's not only conceptually better but the listening experience is also significantly improved.
Image #1
I made a simple IP (the FIR_compiler + a bram block to time-align each speaker) with 4 inputs:
- sys_clk = 100MHz Fabric clock
- spdif_clk = 128fs
- to_fir = signed 16-bit audio sample (lower 16 bits=left channel, higher 16 bits=right channel)
- reset = to ensure all the IP individual SPDIF counters start counting at the exact same time
and one output: the SPDIF EMIO
Then it's pretty straightforward to go bi/tri/quad... amps
Image #2
The measurements of my right channel:
- upper part = each amp separately
- light blue below (graphically dragged down a bit to be able to distinguish it) = all 4 amps
The FIR compiler coefficients are calculated from
(I made the slope pretty stiff for horn drivers)
attached are the VHDL source files.