FPGA Design

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Zynq docoumentation

by aolofsson » Thu Apr 17, 2014 3:26 pm

Replies: 0

Views: 15024

Thu Apr 17, 2014 3:26 pm

by aolofsson View the latest post

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Figuring out where addresses comes from?

by mkaczanowski » Mon Feb 17, 2020 8:47 pm

Replies: 0

Views: 95

Mon Feb 17, 2020 8:47 pm

by mkaczanowski View the latest post

Generate bitstream with Vivado 2019.x

by mkaczanowski » Mon Feb 10, 2020 10:31 pm

Replies: 2

Views: 165

Mon Feb 17, 2020 8:13 pm

by mkaczanowski View the latest post

Vivado(_hls) 2019.2 , Anyone ?

by theover » Sat Dec 07, 2019 12:25 pm

Replies: 7

Views: 2026

Wed Jan 08, 2020 5:16 pm

by theover View the latest post

creating a output register/interrup from PL to arm processor

1, 2

by dipin » Tue May 29, 2018 12:30 pm

Replies: 11

Views: 37498

Wed Nov 07, 2018 12:01 am

by cpantel View the latest post

how to add push button to GPIO?

by parallella-project » Mon Aug 13, 2018 1:39 pm

Replies: 2

Views: 6553

Fri Aug 17, 2018 1:57 am

by olajep View the latest post

no device detected using jtag

by parallella-project » Thu May 31, 2018 11:32 am

Replies: 1

Views: 5196

Fri Jun 08, 2018 2:15 pm

by olajep View the latest post

Synthesis Error:loop statement with empty body is not permit

by Min » Sat Jun 02, 2018 1:33 am

Replies: 1

Views: 5101

Wed Jun 06, 2018 5:25 am

by dipin View the latest post

error after make command to build a vivado project

by parallella-project » Mon May 28, 2018 5:39 am

Replies: 6

Views: 11346

Tue Jun 05, 2018 5:18 pm

by Min View the latest post

parallella desktop edition: fpga to arm processor interrupt

by dipin » Tue Jun 05, 2018 5:20 am

Replies: 1

Views: 5183

Tue Jun 05, 2018 5:01 pm

by Min View the latest post

how to install uio drivers in parallella board

by dipin » Thu May 10, 2018 1:47 pm

Replies: 1

Views: 5893

Sun May 20, 2018 6:42 am

by Min View the latest post

using headless kernal in parallella fpga with an hdmi

by dipin » Wed May 16, 2018 5:46 am

Replies: 2

Views: 6042

Thu May 17, 2018 10:03 am

by olajep View the latest post

Xilinx Design Constraint

by parallella-project » Wed May 16, 2018 4:16 pm

Replies: 1

Views: 4823

Thu May 17, 2018 9:17 am

by olajep View the latest post

where has parallella vivado project been moved in github?

by parallella-project » Wed Mar 07, 2018 3:39 pm

Replies: 3

Views: 10962

Thu Mar 29, 2018 6:16 am

by Min View the latest post

Attachment(s) Open source GPU

by minkanjin » Sat Jun 04, 2016 7:39 pm

Replies: 3

Views: 11987

Mon Sep 25, 2017 3:46 pm

by adexmont View the latest post

Attachment(s) FPGA Accelerator

by promach » Tue Jan 03, 2017 7:47 am

Replies: 5

Views: 18323

Tue Sep 05, 2017 3:20 pm

by olajep View the latest post

Attachment(s) Isn't there any board file for Parallella to use in Vivado?

by parallella-project » Fri May 19, 2017 2:01 pm

Replies: 7

Views: 21003

Wed Aug 16, 2017 10:43 pm

by frankbuss View the latest post

github asicguy gplgpu --> FPGA 7020

by adexmont » Sat Aug 05, 2017 9:38 am

Replies: 1

Views: 7118

Mon Aug 14, 2017 5:27 pm

by sebraa View the latest post

Troubles rebuilding the FPGA

by avignani » Fri Sep 16, 2016 11:20 pm

Replies: 5

Views: 13697

Wed Aug 09, 2017 4:36 pm

by frankbuss View the latest post

PL fabric clock

by a_k » Wed Feb 17, 2016 9:52 am

Replies: 8

Views: 21692

Sat Aug 05, 2017 4:43 pm

by MelHance View the latest post

Attachment(s) Why does Oh! Library AXI convert between eMesh and Packets

by ninlar » Wed Jun 21, 2017 11:57 pm

Replies: 9

Views: 23304

Fri Jun 30, 2017 2:05 pm

by olajep View the latest post

Cannot boot after adding FPGA accelerator

1, 2

by jimmystone » Sun May 21, 2017 9:14 am

Replies: 10

Views: 26316

Thu Jun 22, 2017 3:14 pm

by sebraa View the latest post

Attachment(s) risc-v and such

by jlambrecht » Sun Jun 05, 2016 7:42 pm

Replies: 7

Views: 19259

Thu May 25, 2017 3:12 pm

by promach View the latest post

Timing violation of Parallella PFGA project

by jimmystone » Sun May 21, 2017 8:58 am

Replies: 0

Views: 5601

Sun May 21, 2017 8:58 am

by jimmystone View the latest post

LEON3 CPU - FPGA

by bgeorge » Tue Apr 18, 2017 12:33 pm

Replies: 2

Views: 8165

Wed Apr 19, 2017 11:19 am

by bgeorge View the latest post

When using EMIO do I need to rebuild the FSBL

by wiegmink » Thu Mar 30, 2017 1:31 pm

Replies: 2

Views: 7389

Sat Apr 01, 2017 1:48 pm

by olajep View the latest post

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