7010 FPGA design files

[theover]

Hi,

I was installing Vivado (the latest Xilinx design tools) on my Fedora 18/64 system today, with as the purpose to recompile some stuff I want to try out on both my Spartan 3e board and (once it gets there) the Parallella, and to try out running the "standard design" for the Parallella FPGA, to make my own bit files.

I couldn't find the pin count (nor strictly speaking the speed variation, but I presume it's -1 like the Zinq 7020), and also not a "top" module for the 7010 variation, and strangely enough also not a single picture I could find that states the exact chip number!

Is there some way currently to get the up to date, working actual design that's in the current 7010 based Parallella boards in verilog form, and some sort of guide where the stub-files go, because just loading in the 7020 .v . udf and .xc files from Git didn't look very good, is there a complete project zip for instance ? I presume one has been made, considering there are working 7010 boards on the markets, in the spirit of the OS it shouldn't be too hard to zip the used project.

I'll have to download ISE 14.7 tomorrow, too, and check out my Spartan 3e design, so maybe I'll have another look, but either I've been using the wrong files, or I'm missin gsomething here.

T.

[FHuettig]

Hi T,

The part used on the 7010 Parallellas is xc7z010clg400-1 (7020 board uses xc7z020clg400-1). The parallella-hw repository was just updated to add projects that may help you, see:
viewtopic.php?f=10&t=1069

The repository is here:
https://github.com/parallella/parallella-hw

The top-level hdl file is fpga/hdl/parallella-I/parallella_z7_top.v, and supports both the 7010 and 7020 depending on the definition of either kTARGET_7Z010 or kTARGET_7Z020 in the global version.v file. The only difference between the two is a set of 12 differential GPIO pairs, which are currently unused anyway.

-Fred

[theover]

Alright, cool, I'll have a look at that.

T.

[theover]

So far, I've included all verilog source files I felt would be appropriate into ISE 14.7 (webpack).

I think the "defines" in the include files (like version.v or fpga_constants) aren't used, so the design cannot know if it's a 7010 or 7020, and if there'll be a hdmi circuit or not, but I presume the default will be ok for now. I just wondered where I should put the extra includes, probably just in the top module isn't enough, or is it.

Anyway, now I have the whole project, there's one fly in the soup: in system_sub, symbol "system_i" is missing!

Should I read the verilog and figure it out, or can anyone give a quick answer to get me to try an compile my own bit-file ?

T.

[FHuettig]

The way it's handled in the planahead projects is that version.v and fpga_constants.v are marked as global so they get included everywhere by default. This is left over from the codebase I inherited, I agree it's not a particularly portable way of handling things (no disrespect to the author, who did a great job of getting everything going). I'll update this today to make those files real headers (change extension to .vh) and add the `includes as needed. There are other stylistic things I may change too going forward, the immediate goal was to get a snapshot of the existing codebase.

About system_stub.v, that is generated by XPS and again the planahead projects take care of it, but you can find a built version in the repository under:

parallella-hw/fpga/projects/parallella_7010_headless/parallella_7010_headless.srcs/sources_1/imports/parallella_7010_headless/

The 7020 and E64 projects each have copies too.

To be honest I'm not sure how ISE deals with the Zynq PS block, you may need a netlist that xps generates and/or the constraints file. I'll reply back here when I've fixed the include file issues and please let me know what else you need.

-Fred

[theover]

I'll have a look if I can make global defines in ISE 14.7 or the latest Vivado.

I imported the "stub" but it got not recognized, if it isn't necessary, maybe I can run the project anyway. Will try.

It's interesting to have the whole design running for when the board comes, but some parts must be done right, and accurate: I don't want to run the risk of blowing the board up and waiting so-much-more time!

T.

[FHuettig]

Hi T,

I haven't been ignoring this, but there has been some philosophical discussion here about the way we want to handle this sort of thing with sources. I verified that ISE 14.7 understands the concept of a global include file, It's not an option when the source is first added to the project but once it's there you can right-click on the file in the hierarchy, select "Source Properties" and then check the box "Include as global file." So at least for now we're going to keep the sources the way they are and require new projects to mark both "version.v" and "fpga_constants.v" as global files, then fix the compile order if the tools don't recognize that "version" has to come before "fpga_constants." I may revisit this again in the future.

I wasn't able to do a build with ISE either because of the system black box module, even after adding the xps-generated system.ngc file to the project. I'm sorry but I'm not going to pursue this further because we have a usable solution with PlanAhead and the next intended step is to move forward to Vivado. Is there a reason you want to use ISE directly rather than starting with the existing PlanAhead project? I think if you poke around PlanAhead a bit you can find anything you are used to doing with ISE, but let me know if that's not true.

I appreciate your caution with the new board! As long as you keep the pins that go to the Epiphany configured in the proper directions you should not be able to cause any damage. Starting with the constraints files and top-level verilog from our projects should keep you quite safe.

-Fred

[theover]

All I'd like to begin with when hopefully any day now (...), I get a message that the 7010 schedule is only so-far behind that I can get mine, is to have a downloadable set of source files, or as is non un-common, a ISE (or Vivado) project zip with all needed files, that have been tested to give a certain .bit file, which has been tested by you guys to work good.

I'll then try to compile that myself (I had my big system ready for that a while ago), and try to make some additions, as I can use for possible future projects.

My point being, I know from working some on a FPGA processor design that it isn't a given that getting a system for FPGA through the silicon compilation, and some usually rudimentary simulation tests, guarantees that the resulting system downloaded to the FPGA will work reliable in various boards (especially if there are revisions). I don't mind testing some stuff out, like doing some interesting FPGA additions, as was my original intention (in line with the initial Parallella project description I subscribed to), but I need to start with a design which is bit more than a set of design file copies trickled down from an licensed EDI design environment, to satisfy the Open Source though. It needs to work, and I don't want to be dumbed down to have to make all kinds of exclusions.

T.

[FHuettig]

Hi T.,

You can get all the source files and project files directly from github:

It's best if you clone the repository locally, but you can also download a zip file of everything if you don't want to deal with git. However, in order to compile the hdmi-enabled version you'll need to also grab another github repository. Using git makes that second step easy, without git you'll have to download another zip file and extract everything in the right place.

These are not dumbed-down or limited in any way, these are the exact projects & sources we use here and what we put in the newer distributions.

Start with the project file that is closest to what you want, either headless or hdmi, from the fpga/projects directory. Read the README file in that project directory for additional instructions. Feel free to respond back here with any issues you run into.

-Fred

[theover]

I've downloaded the latest repository yesterday, let ISE14.7 rip for 3 minutes (On Fedora 18/64), tested the non-hdmi .bit file, and it worked. I didn't look at the ~250 warnings, nor at all the timing figures yet.

The lower clock frequency of the IO to the Epiphany is of course a consideration, the only upside being that my fan-less board, with extra aluminum cooling surface, stays a lot cooler.