Bare metal application with FPGA co-processor

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Re: Bare metal application with FPGA co-processor

Postby aolofsson » Fri May 20, 2016 6:48 pm

Great stuff. Thanks for posting this on the forum!

Timing paths:
Based on where those paths are, those paths go to the reset synchronizer. I probably declared those as false paths and forgot to check them in to the constraints back in the fall.

Master:
Master branch needs to be updated to new oh modules for fifos. (either a path issue or a module rename issue)

Yes, your summary sounds good.

Andreas
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Re: Bare metal application with FPGA co-processor

Postby eliaskousk » Fri May 20, 2016 7:20 pm

Andreas thank you for the quick reply.

So it seems I have built a good bitstream with vivado 2015.4 and this version can be used for Parallela bitstreams.

Can't wait to try it out on the board!

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Elias
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