Vivado project for headless 7020

[boeserbaer]

HI All,

I am working on a Vivado (14.2) port of the parallella headless design. I am done getting the CPU MIO/DDR settings in place, and have packaged the parallella e-link ip.

I am a little confused regarding address options. I am expecting to see the DDR as a 1GB entry starting at 0. I also don't know quite what to do with the elink addressing particularly the HP1 slave port.

Part of the confusion is that I am an ISE user till now, and previously a Quartus user.
All of the Vivado tutorials I see are using the block design mode. Am I making a mistake to try to create a black based design?

Any suggestions?

Mike Ingle