Skyscraper-style carbon-nanotube chip design
Posted: Sat Dec 12, 2015 11:34 amParallella Community
Supercomputing for Everyone
https://parallella.org/forums/
Skyscraper-style carbon-nanotube chip design
Page 1 of 1
Posted: Sat Dec 12, 2015 11:34 amRe: Skyscraper-style carbon-nanotube chip design
Posted: Sun Dec 13, 2015 10:38 amafaik something like that is on adapteva's roadmap...
Re: Skyscraper-style carbon-nanotube chip design
Posted: Wed Dec 16, 2015 4:42 pmstacked memory.. huge amounts of per core memory would be a game changer for a scratchpad/NoC machine.
But what about a full on 3D grid further down the line- how much seperation would you need between processor layers for cooling. how would it change potential inter-core distances if you could route in 3 dimensions, for the same area of transistors, is the potential benefit comparing N^(1/2) vs N^(1/3) ?
assuming a square core with separated vertically by its' 'side', making a cube..
e.g. 64 cores as 8x8 vs 4x4x4 .. half the average inter-core distance?
4096 cores as 64x64 vs 16x16x16 .. 1/4 the distance for the same array?
262144 cores as 512x512 vs 64x64x64 .. 1/8th the distance..
lets say the average PC today has 2billion processor transistors + 16gb ram; as a cube of silicon would that translate into 16x16x16 x 488K transistors per little-core, 4Mb per core scratchpad, 3x16 'cycles' hop between opposite corners, (today, 100ns from CPU to main memory? would you bring 16gb within 10ns with full 3d NOC tech?)
on a simpler level could you make server boards that were 3d stackable e.g. 4x4 chips x 4 boards with 16 vertical 'elevators' for 3d connection..
But what about a full on 3D grid further down the line- how much seperation would you need between processor layers for cooling. how would it change potential inter-core distances if you could route in 3 dimensions, for the same area of transistors, is the potential benefit comparing N^(1/2) vs N^(1/3) ?
assuming a square core with separated vertically by its' 'side', making a cube..
e.g. 64 cores as 8x8 vs 4x4x4 .. half the average inter-core distance?
4096 cores as 64x64 vs 16x16x16 .. 1/4 the distance for the same array?
262144 cores as 512x512 vs 64x64x64 .. 1/8th the distance..
lets say the average PC today has 2billion processor transistors + 16gb ram; as a cube of silicon would that translate into 16x16x16 x 488K transistors per little-core, 4Mb per core scratchpad, 3x16 'cycles' hop between opposite corners, (today, 100ns from CPU to main memory? would you bring 16gb within 10ns with full 3d NOC tech?)
on a simpler level could you make server boards that were 3d stackable e.g. 4x4 chips x 4 boards with 16 vertical 'elevators' for 3d connection..