MEMSYS 15 Conference Program

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http://memsys.io/program/

JUST FYI, time is ticking.

Monday, October 5th

5:00 pm – Evening Welcome Reception

Tuesday, October 6th

7:30 am – Breakfast in the Hotel Restaurant

8:40 am – Opening Remarks

9:00 am – Keynote: J. Thomas Pawlowski, Micron
Chief Technologist / Micron Fellow
Architecture Development

10:00 am – Break

10:20 am – Session 1: Opportunities and Challenges

10:20 – Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
Gabriel H. Loh (Advanced Micro Devices), Natalie Enright Jerger (Advanced Micro Devices and University of Toronto), Ajaykumar Kannan (University of Toronto), Yasuko Eckert (Advanced Micro Devices)
10:40 – Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore
Syed Minhaj Hassan (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Saibal Mukhopadhyay (Georgia Institute of Technology)
11:00 – Opportunities and Challenges of Performing Vector Operations inside the DRAM
Marco A. Z. Alves (Federal University of Rio Grande do Sul), Paulo C. Santos (Federal University of Rio Grande do Sul), Matthias Diener (Federal University of Rio Grande do Sul), Luigi Carro (Federal University of Rio Grande do Sul)
11:20 – SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype
Chad D. Kersey (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology)
11:40 – Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC? Milan Radulovic (Barcelona Supercomputing Center & Universitat Politècnica de Catalunya), Darko Zivanovic (Barcelona Supercomputing Center & Universitat Politècnica de Catalunya), Daniel Ruiz (Barcelona Supercomputing Center), Bronis R. de Supinski (Lawrence Livermore National Lab), Sally A. McKee (Chalmers University of Technology), Petar Radojkovic (Barcelona Supercomputing Center), Eduard Ayguade (Barcelona Supercomputing Center)
12:00 pm – Conference Lunch

1:00 pm – Session 2: Rethinking Architectures and Design Approaches

1:00 – A Data Centric Perspective on Memory Placement
Yitzhak Birk (Technion), Oskar Mencer (Maxeler Technologies)
1:20 – The Semantic Gap Between Software and the Memory System
Jim Stevens (University of Maryland), Paul Tschirhart (University of Maryland), Bruce Jacob (University of Maryland)
1:40 – MMC: a Many-core Memory Connection Model
Chen Ding (University of Rochester), Hao Lu (University of Rochester), Chencheng Ye (University of Rochester)
2:00 – High Performance Computing Co-Design Strategies
James A. Ang (Sandia National Laboratories)
2:20 pm – Break

2:40 pm – Session 3: The Devil is in the Details

2:40 – Opportunities to Upgrade Main Memory
Dave Resnick (Sandia National Laboratories)
3:00 – E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems
Hsing-Min Chen (Arizona State University), Akhil Arunkumar (Arizona State University), Carole-Jean Wu (Arizona State University), Trevor Mudge (University of Michigan), Chaitali Chakrabarti (Arizona State University)
3:20 – Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design
Ali Eslami (Duke University), Alfredo Velasco (Duke University), Alireza Vahid (Duke University), Georgios Mappouras (Duke University), Robert Calderbank (Duke University), Daniel Sorin (Duke University)
3:40 – Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes
Bruce R. Childers (University of Pittsburgh), Jun Yang (University of Pittsburgh), Youtao Zhang (University of Pittsburgh)
4:00 – Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs
Matthias Jung (University of Kaiserslautern), Éder Zulian (University of Kaiserslautern), Deepak M. Mathew (University of Kaiserslautern), Matthias Herrmann (University of Kaiserslautern), Christian Brugger (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Norbert Wehn (University of Kaiserslautern)
4:20 pm – Break

5:00 pm – Spirited Discussion: Memory Systems Problems and Solutions
(over beer, wine, and hot hors d’oeuvre)

Hillery Hunter, IBM
Mike Ignatowski, AMD
Aamer Jaleel, NVIDIA
Dave Resnick, Sandia
Dave Wang, Inphi
7:00 pm – Dinner on your own

Wednesday, October 7th

7:30 am – Breakfast in the Hotel Restaurant

8:40 am – Invited Session: Memory as an Enabling Technology for Exascale Systems — DOE and NSA Perspectives

Thuc Hoang, NNSA
Thomas Salter, ACS
TBD
10:00 am – Break

10:20 am – Session 4: Caches and Software Management of Memory

10:20 – Implications of Memory Interference for Composed HPC Applications
Brian Kocoloski (University of Pittsburgh), Yuyu Zhou (University of Pittsburgh), Bruce Childers (University of Pittsburgh), John Lange (University of Pittsburgh)
10:40 – Software Techniques for Scratchpad Memory Management
Paul Sebexen (REX Computing), Thomas Sohmers (REX Computing)
11:00 – Dynamic Memory Pressure Aware Ballooning
Jinchun Kim (Texas A&M University), Viacheslav Fedorov (Texas A&M University), Paul V. Gratz (Texas A&M University), A.L. Narasimha Reddy (Texas A&M University)
11:20 – Shared Last-Level Caches and the Case for Longer Timeslices
Viacheslav V. Fedorov (Texas A&M University), A. L. Narasimha Reddy (Texas A&M University), Paul V. Gratz (Texas A&M University)
11:40 – S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing Applications
Reza Mokhtari (University of Toronto), Michael Stumm (University of Toronto)
12:00 pm – Conference Lunch

1:00 pm – Session 5: Design and Simulation Methodologies

1:00 – Architecture Exploration for Data Intensive Applications
Fernando Martin del Campo (University of Toronto), Paul Chow (University of Toronto)
1:20 – MEMST: Cloning Memory Behavior Using Stochastic Traces
Ganesh Balakrishnan (Advanced Micro Devices), Yan Solihin (North Carolina State University)
1:40 – Modeling Data Movement in the Memory Hierarchy in HPC Systems
Aditya M. Deshpande (Information Sciences Institute, University of Southern California), Jeffrey T. Draper (Information Sciences Institute, University of Southern California)
2:00 – Rethinking Design Metrics for Datacenter DRAM
Manu Awasthi (Samsung Semiconductor)
2:20 pm – Break

2:40 pm – Session 6: Multi-Level and Hybrid Main Memories

2:40 – HpMC: An Energy-aware Management System of Multi-level Memory Architectures
ChunYi Su (Virginia Tech), Edgar A. Leon (Lawrence Livermore National Laboratory), Gabriel Loh (Advanced Micro Devices), David Roberts (Advanced Micro Devices), Kirk W. Cameron (Virginia Tech), Dimitrios S. Nikolopoulos (Queen’s University of Belfast), Bronis R. de Supinski (Lawrence Livermore National Laboratory)
3:00 – Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance
Paul Tschirhart (University of Maryland), Jim Stevens (University of Maryland), Zeshan Chishti (Intel Labs), Shih-Lien Lu (Intel Labs), Bruce Jacob (University of Maryland)
3:20 – The Potential and Perils of Multi-Level Memory
Jagan Jayaraj (Sandia National Laboratories), Arun Rodrigues (Sandia National Laboratories), Simon Hammond (Sandia National Laboratories), Gwendolyn Voskuilen (Sandia National Laboratories)
3:40 – k-Means Clustering on Two-Level Memory Systems
Michael A. Bender (Stony Brook University), Jonathan Berry (Sandia National Laboratories), Simon D. Hammond (Sandia National Laboratories), Branden Moore (Sandia National Laboratories), Benjamin Moseley (Washington University), Cynthia A. Phillips (Sandia National Laboratories)
4:00 – Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories
Ahsen J. Uppal (The George Washington University), Mitesh R. Meswani (Advanced Micro Devices)
4:20 pm – Break

5:00 pm – Spirited Discussion: New and Cool Memory Technologies (HBM and HMC)
(over beer, wine, and hot hors d’oeuvre)

Wendy Elsasser, ARM
Jaejin Lee, SK Hynix
Gabriel Loh, AMD
Mike O’Connor, NVIDIA
J. Thomas Pawlowski, Micron
7:00 pm – Conference Dinner

Thursday, October 8th

7:30 am – Breakfast in the Hotel Restaurant

8:40 am – Session 7: A Focus on Applications

8:40 – Anatomy of GPU Memory System for Multi-Application Execution
Adwait Jog (College of William and Mary), Onur Kayiran (Advanced Micro Devices), Tuba Kesten (The Pennsylvania State University), Ashutosh Pattnaik (The Pennsylvania State University), Evgeny Bolotin (NVIDIA), Niladrish Chatterjee (NVIDIA), Stephen W. Keckler (NVIDIA and UT Austin), Mahmut T. Kandemir (The Pennsylvania State University), Chita R. Das (The Pennsylvania State University)
9:00 – Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads
Anouk Van Laer (University College London), William Wang (ARM Research), Chris Emmons (ARM Research)
9:20 – Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion
Zhaoxia Deng (University of California, Santa Barbara), Lunkai Zhang (University of California, Santa Barbara), Diana Franklin (University of California, Santa Barbara), Frederic T. Chong (University of California, Santa Barbara)
9:40 – Instruction Offloading with HMC 2.0 Standard — a Case Study for Graph Traversals
Lifeng Nai (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology)
10:00 am – Break

10:20 am – Session 8: Systems and Techniques for In-Memory Processing

10:20 – Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data Analytics
I. Stephen Choi (Samsung Semiconductor), Yang-Suk Kee (Samsung Semiconductor)
10:40 – NCAM: Near-Data Processing for Nearest Neighbor Search
Carlo C. del Mundo (University of Washington), Vincent T. Lee (University of Washington), Luis Ceze (University of Washington), Mark Oskin (University of Washington)
11:00 – Understanding Energy Aspect of Processing Near Memory for HPC Workloads
Hyojong Kim (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Arun Rodrigues (Sandia National Laboratories)
11:20 – Near Memory Data Structure Rearrangement
Maya Gokhale (Lawrence Livermore National Lab), Scott Lloyd (Lawrence Livermore National Lab), Chris Hajas (University of Florida)
11:40 am – Closing Remarks