now that this technology is ages old, anyone has some news on that, in relation to parallella? since parallella needs a redesign anyway, could this technology be used there? or in the new redesigned epiphany4 chip?
as for an epiphany5, I was thinking, what about a 3d-mesh network, with north,south,east,west, and up and down? maybe a pin-out allowing for 6 elink connections? 12GB/s, 6 in and 6 out, that sounds quite interesting. well, maybe not for 64 cores, but 4096 cores based on a 16x16x16 grid sounds much more managable than a 64x64 network. maybe even give fpga access to 3 elink-connections instead of 1...
of course my ideas wont work: heat-management in 3d is much more complicated. and there simply is not enough space for 150% pins (so I guess epiphany and fpga need to talk spi to eachother). but at least I can dream.