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Parallella Community • View topic - Generate bitstream with Vivado 2019.x

Generate bitstream with Vivado 2019.x

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Generate bitstream with Vivado 2019.x

Postby mkaczanowski » Mon Feb 10, 2020 10:31 pm

mkaczanowski
 
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Re: Generate bitstream with Vivado 2019.x

Postby olajep » Wed Feb 12, 2020 12:24 am

The fixes for that should be in my master branch here:
https://github.com/olajep/oh.git

That version is for Vivado 2018.2. You need to edit the block design scripts:
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23
https://github.com/olajep/oh/blob/b57c7 ... bd.tcl#L23


The ADI IP's require Vivado 2018.2 so the HDMI bitstream builds will likely break.
You should be able to override that with "export ADI_IGNORE_VERSION_CHECK"

HTH,
Ola
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olajep
 
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Location: Sweden

Re: Generate bitstream with Vivado 2019.x

Postby mkaczanowski » Mon Feb 17, 2020 8:13 pm

Thanks a lot that helped. I tried with the older version 2018.2 and it works fine.
mkaczanowski
 
Posts: 4
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