Parallella Community

Is there any board file for parallella (like zedboard, zybo or ...) to use for configuration of Vivado at the start of creating a project (when choosing the development board)?
I mean add Parallella board to this dialogue:

That's just an FPGA chip chooser. Pick one of the "boards" and adjust accordingly. Main reason I can think of for it not having a "board" file is because they're not Digilent or Avnet. Xilinx works with them quite tightly- and none of this gets into the reality that you're not going to have a "board" file for a design you make in the first place. You're going to pick a rough board or the FPGA chip you know is on your device. You're not going to get a board file for anything other than an Arty on Artix setups, for example...

not sure this is what you r looking for but may be one of the way :
I cloned parallella-fpga github repository and installed vivado 2017.2 web (free) version.
I opened a new project in the cloned folder and retrieving the parallella source from there.

Vivado looks like simulate quite well all the steps (not able to say if any of that warning may be critical)

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [Runs 36-53] Possible issues detected after target generation. Generation state is unexpected for target 'Simulation'. Expected 'Generated', got 'Stale' for source '/home/user /parallella/parallella-fpga/adexparallella/adexparallella.srcs/sources_1/bd/base_zynq/base_zynq.bd'

This was the 3 ones marked in red that may provide some hint for some critical issues.

I ask here but please reply in post Can anyone point me in whitch part the "gpu/bitstraem" already in use is described/implemented ?

Thanks

I ported the accelerator to Vivado 2017.2. Looks like this version is a bit more picky about missing wires etc., needed some fixed in OH components. These are the differences:

https://github.com/FrankBuss/oh/commit/ ... 807ceceefb

The system_bd.tcl file was just re-created by Vivado as suggested from the script, with "write_bd_tcl" on the Tcl command line. I guess it would be as easy with the parallella project.

BTW, I noticed the OH components are very unfinished, like there is a lot of empty modules and skeleton code. Is this project still alive and do people write code for it? Personally I don't like Verilog, I prefer VHDL. But recently I discovered Chisel ( ), which makes it much easier to write HDL programs, because it has the power of Scala as the backend. For example exhaustive testbenches are much simpler to write and run. Or need a ROM with a sin-table? No problem with a real language like Scala, just one line to generate it inline for the synthesizing step. This might be a better base for the OH framework.