Example DMA design (Vivado 2015.4)
Posted: Sat Jan 30, 2016 7:40 am
I have written a tutorial on how to do DMA transfer in and out of PL (Vivado 2015.4)
Repository linked above includes Python library and a test app that interfaces with AXI DMA via UIO driver.
While the design I used as an example is a simple loopback, MM2S is connected to S2MM via a FIFO buffer, the same approach can be used for connecting more advanced accelerators, just replace the FIFO with your IP block.
Repository linked above includes Python library and a test app that interfaces with AXI DMA via UIO driver.
While the design I used as an example is a simple loopback, MM2S is connected to S2MM via a FIFO buffer, the same approach can be used for connecting more advanced accelerators, just replace the FIFO with your IP block.