A few requests for the FPGA design

[tnt]

Hi,

Here's a list of what I'd like to see happen :

* Better encapsulation

By this I mean both refrain to use too generic names. I mean 'axi_master' is a pretty generic name for something that's completely specific to the eLink. I think something like emesh_axi_master or elink_axi_master would be more appropriate.

I also mean that the whole AXI <-> eMesh should be a module in itself, something pretty self contained that can be copied to another project. Currently you have to copy several subdirs and correctly interconnect them. Or maybe that's what parallella.v is supposed to be ? But then I would still comment that the name isn't great (because it's just the elink part and not the whole parallella design) and I'd make sure the directory reflects that (i.e. don't have the parallella_z7_top.v top level in the same dir).

Something like :

hdl/
top/
parallella_z7_top.v
elink/
elink_top.v
axi/...
phy/...
utils/...

So that you can easily just copy elink/ to your own project, wire the two AXI to the PS7 and the other wires to the pads and you get a working elink in your project.

This could even be a submodule with it's own vivado tcl script to set-it up so that updates are easier.

* Improved compatibility with the Rev 0 board.

Using generic (or whatever the verilog equivalent is), it should be fairly straight forward to have this AXI <-> eMesh wrapper to support both Rev0 and Rev 1.x boards. They might not be the best from a power PoV but they work just fine and it's a bit of a waste not to allow those who have some to use it.

* Work with the Vivado flow

My last attempt at this yielded some 'logic loop' during synthesis ... no idea what was going on since my verilog isn't all that good (I'm a VHDL guy


Cheers,

Sylvain

[aolofsson]

sylvain,
Great inputs! A hierarchy reorg and moving to vivado are on the very soon todo list. We are still trying to check off one thing at a time...
Andreas

[bithead]

I'd like to request a "nice-to-have" thing for us FPGA hobbyists that are also somewhat (less than 3 years of hobbyist exp) new to the whole hardware design thing --

An example project that shows how to add our own designs alongside the Parallella eLink stuff. The warnings about pin constraints are kind of dire and scare people like me; if there was a sample project that added something to the design that I could use as a base for my own design, or maybe even just a blank template I could use as a starting point, I'm sure a lot of us who bought the Parallella for more than just the Epiphany chip would be very happy.

[xilman]

[Transcendental]

[FHuettig]

[FHuettig]

[tnt]

[over9000]

I'm sorry if this is a very newbie question, but if I wanted to change part of the FPGA logic, would it be possible to simply write some new code to target unused parts of the chip (pins + logic), or does the entire bitstream (plus my modifications) need to be recompiled at the same time? If it's the latter, is a reboot needed to reprogram the FPGA?

[FHuettig]