Parallella Community

Hi,

In the 'building linux image' guide recently released, I don't see any mention of the executable that AFAIU programs the clock generator on the epiphany FMC. Is that not needed for operation ?

Cheers,

Sylvain

Hi Sylvain,

The core clock for the Epiphany chip on the FMC board is a fixed frequency clock driven by a clock generator on the FMC card (600MHz). The HDL build guide written by Roman explains how to create the clock frequency for the FPGA logic (including the Epiphany link interface).

http://www.adapteva.com/white-papers/pa ... ce-design/

The final Parallella design will have a clock frequency that is programmable directly from the FPGA logic.

Andreas

I was talking about /home/linaro/work/scr/lclk_div4.elf that's called at boot time in the pre-made image.

That's not required ?

Sylvain,

That lclk divide program should be considered a temporary patch, because the link from the Epiphany to the Zynq currently does not work up to 300MHz. We need the divide by 4 to get the link clock down to 150MHz.

The rc_local method was not ideal, we are just now in the processing of putting that patch in the system reset sequence code. Obviously the plan is to get rid of it all together once we have the system ramped up and running.

Thinking of it now, if you were resetting the board during your work without power cycling the board, then the lclk divide settings would have been deleted, and could lead to the issues you were seeing with the DMA...

Andreas