Can fpga response elink out-of order?
Posted: Sat Nov 09, 2013 3:25 amHi, All
I just have a question about elink read response timing.
For example, epiphany issue two read request to two different address. reqA and reqB
Can the response data DataB come back first? or FPGA must send back DataA first?
I just have a question about elink read response timing.
For example, epiphany issue two read request to two different address. reqA and reqB
Can the response data DataB come back first? or FPGA must send back DataA first?