direct memory access possible?

[notzed]

[Gravis]

[LamsonNguyen]

I, for one, would want to mess around with a 4096 core Epiphany, even if it weren't real.

[Gravis]

@ysapir
can i get a response to my post? viewtopic.php?f=23&t=574#p3517

[tnt]

it seems pretty clear that you can't have a full 4096 core ... the (0,0) is always mapped to the local one and any directly mapped external memory is just accessed by the same routing N/S/W/E that any other core and so you need to reserve space for that. (by stealing some from possible cores).

Your "magical" unregister of a core just doesn't make much sense in the current chips and it would imply quite a bit of logic in each router node to know and keep track of this. Any way to grow beyond the current model would need to sacrifice the 'uniform' address space view and would most likely be implemented by translation layers between 'islands' of cores, avoiding to modify the mesh and cores themselves and just adding logic at the edge of large groups of them.

[ticso]

Beside the 0,0 core you should have a square setup with all rows and all columns of the same size, so idially you would either not populate 0 row or 0 column completely.
If you don't have a full setup not every core can communicate with every other core because of static routing.
With 64 core chips you loose more cores of that theoretical 4k space as not having row 0 means not having other rows as well.
You also need some addressable space to communicate with external components.
External communication with square layout is already reduced because of routing limitations.