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Parallella Community • View topic - dual instruction execution behavior

dual instruction execution behavior

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Re: dual instruction execution behavior

Postby EggBaconAndSpam » Mon Aug 05, 2013 12:27 pm

or just think of the registers as transparent latches. http://en.wikipedia.org/wiki/Latch_(electronics)#Gated_latches_and_conditional_transparency
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Re: dual instruction execution behavior

Postby Gravis » Mon Aug 05, 2013 5:25 pm

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Re: dual instruction execution behavior

Postby EggBaconAndSpam » Mon Aug 05, 2013 6:02 pm

Do remember that there is one thing, gpgpus aren't good at: branching/indirection.
Function pointers and stuff might work better on cpus.
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Re: dual instruction execution behavior

Postby Gravis » Mon Aug 05, 2013 6:13 pm

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