dual instruction execution behavior

[Gravis]

[EggBaconAndSpam]

1. no, the core doesn't ever wait for any one operation to complete, unless a dependency stall occurred (this is related to how pipelining works, doesn't behave differently with dual-issuing)
2. unless there is a register dependency or resource contention, neither operation waits. there are two independent pipelines running simultaneously
3. yes
4. only register dependency. note, however, that two FALU instructions can't be dual-issued as they share the same execution unit

[Gravis]

[EggBaconAndSpam]

Not quite sure what you are pointing at.
Consider the "pipeline" just 8 execution units.
Each cycle one pipeline finishes (reaches E4) and another one gets fed an opcode (FE state).
Effectively 8 instructions are run in parallel, this way one instruction is issued per cycle (actually two, but that's a different matter).
So what do you mean by FE getting ahead of E4?

[Gravis]

[EggBaconAndSpam]

[Gravis]

[ysapir]

Gravis, it seems to me that you may still have a misconception of what a pipeline stage is (sorry if it is not so). In an N-stage pipeline system, an instruction takes this much cycles to complete. However, several (up to N) instructions are processed concurrently in the pipeline, each of them occupies a single stage. Thus, when an instruction reaches the execution stages, a new instruction is processed in the fetch stages, address generation stages, etc.

If there's no dependency or stalls, then the an instruction execution is concluded at each clock cycle. At the same time, new instruction is fetched, decoded etc. every clock cycle. They all "live" concurrently, but at different stages of "maturity".

[timpart]

The only special wrinkle I've noticed in the pipeline is the the RA register access seems to happen at the "end" of its slot and is in time to read registers written by other instructions in that timeslot (typically at E1 (most instructions), E2 (loads) or E4 (floats) in the pipeline). Otherwise things would take an extra cycle from the published timings.

Tim

[tnt]

My guess would be that the read register can also not read from the regster itself but from a 'bypass' path that gets the value being written rather than what's stored. Then you just have a comparator between the register being read and register being written to know if you need to enable this bypass mode.

But it's just a guess ...