DMA interrupts

[mipt98]

Let's say cores 0 and 1 execute different programs (master/slave type), and core 0 writes to core 1 through DMA0 channel. Is it possible to raise interrupt on core 1 as soon as the data transfer is complete? Seems that E_DMA0_INT is not of big help here...
-Ivan

[hewsmike]

You need to do this in ( your ) software by means of a flag of some sort. Thus the receiving core needs to check the value of that to know when the transfer is finished. This flag will be set by the sending core. The key trick is to have the flag memory location accessed via an atomic instruction that has exclusive access ( briefly ) to said location ( as that technique will avoid various perils ).

The TESTSET instruction has such semantics and you can enact, say, a variety of spin-lock which employs busy waiting by the receiving core.

Cheers, Mike.

[hewsmike]

NB : The TESTSET instruction cannot address below 0x00100000 ie. the memory associated with the core/processor which issued the instruction. So this puts the flag in the receiving node's memory, suitably associated with a transfer buffer being written to.

The receiving node will set this flag to indicate a 'ready for transfer' state, when that becomes true the sending node will set the flag to a 'being transferred' state ( ie. contents of buffer not yet valid ), which when the transfer is finalised sets the flag's value to 'transfer completed' ( buffers contents now valid for use ). When the receiving core wants more data, it'll set the flag to 'ready for transfer' again, etc ...

This is one suitable solution ( off the top of my head ), there may be others of course.

Cheers, Mike.

( edit ) IIRC there was an important correction to the manual as regards the description of TESTSET, which doesn't change my answer, but will make more sense if you have it. Can't remember right now .....

( edit ) TESTSET correction

[hewsmike]

Does anyone have a little flag on their letter boxes anymore? Meaning a physical letterbox outside their house, with a rotatable flag that the postman sets to 'up' position indicating mail has been delivered. When you empty the box - after having recurrently glanced at the flag from inside the house, to see if it's worth going out to pickup the mail - then you reset the flag to 'down'. This is the idea I'm roughly after, with the added refinement of a 'filling' phase.

Cheers, Mike.

[timpart]

It seems there is a not yet fully tested feature to make the DMA cause an interrupt on the remote core (different to the local core ones).

Flags on mail boxes are just an American thing. I guess it is due to land being very cheap and there is a long path from property boundary to front door. The mailbox is on the boundary and the flag lets the householder know it is worth making the trip to it.

Tim

[hewsmike]

Well I guess an interrupt mechanism would avoid busy waiting, allowing the receiving core to ( asynchronously ) check a flag set by the interrupt call. Else you'd have to create distinct paths ( or jumps from ) within the interrupt handler per DMA target - perhaps not wise nor readily extensible. Thanks for that reference

Cheers, Mike.

[mipt98]

E_MESSAGE_INT works!!! Thanks Tim! First I was going to do as Mike suggested -- setting flags and polling, then was thinking about raising soft interrupts after DMA transaction, but then message interrupts fixed everything. So luckily, the feature got released right when it became needed!
-Ivan

[aolofsson]

Nice!! Can't wait to properly release the updated architecture spec with all the new features. Soon...

Andreas

[timpart]

[hewsmike]

@Tim

My reading is much the same. The DMA will plough on asynchronously of the processor - as it no doubt should - so when or even IF the 'channel complete' interrupt is serviced you cannot then assume that the DMA register contents refer to the completed transfer that triggered said interrupt.

Cheers, Mike.

( edit ) Also one has to hope that a higher priority interrupt doesn't want to use DMA either ..... meaning that if it does, even in the absence of chaining, you still won't see the 'right' values in the DMA registers by the time your DMA interrupt service gets to proceed. You could prevent such nesting ( don't follow the initial context save to stack with GIE ) but now you're perverting interrupt priority. Geez Louise I hope we never do multi-threading !