DMA interrupts

[ysapir]

[mhonman]

That sounds very promising - as long as there is no interference/mingling of data streams when several other cores simultaneously send to the target core.

What *does* happen when there are several other cores attempting to act as DMA masters of the same slave? (someone else posted that the data sent by them would be interleaved in an unpredictable manner...)

Thanks
Mark

[ysapir]

Please make the distinction between:

1. Normal SOURCE-DESTINATION DMA copy, where the DMA engine at the TRANSMITTER is active, and,

2. DMA-SLAVE mode, in which the DMA engine on the RECEIVER core is active (the source itself can be, but does not have to be a DMA process. Can be simple memcpy() as well).

In the former case, multiple source cores can DMA data on the destination core. They can write on different destination addresses, or on the same target buffer - where the ultimate data written on a memory location is the last to arrive. If so programmed, then when each of the source DMAs finish, it will generate the MSGMODE interrupt on the destination core. It is your responsibility to orchestrate this mess.

In the latter case, all sources write their data to a single destination address - the destination core's AUTO0DMA register. In this case, every incoming transaction advances the destination pointer to the next location in the memory, according to the DMASTRIDE parameter. Thus, in this case, the order of the incoming transaction is unpredicted and so will be the final buffer - interleaved in an unpredictable manner.

[mhonman]

Thanks for the nice clear explanation, that's the info I need!

And just to reflect my understanding of autodma mode, in that case the slave will continue to accept data from other cores until the buffer defined in its DMA descriptor is full - at which time it will generate a MSGMODE interrupt before moving on to the next DMA desciptor in the chain, if there is one.

[timpart]

[ysapir]