memory access priority/timing

[mhonman]

EBS, Tim posted a very helpful explanation [url viewtopic.php?f=8&t=281&start=10#p2775]here[/url].

As I understand it, there is a single connection between each core and its mesh router, so the aggregate bandwidth available to the core is independent of the number of data transfers that are in progress. Since the connection between core and router is both fast and low-latency, that should not be a limitation in practice. Hopefully I haven't got the wrong end of the stick there...

[Gravis]

i've come to the conclusion that it would be better for the emulator debugger to throw an exception when one of these collision event happens more as a warning than avoiding it's implementation. if you are really going to write that kind of villainous code, you should be testing on the real hardware for indisputable accuracy.

[ysapir]

Gravis, if your program depends on the exact timing of transactions arriving from multiple sources, then you are doing something wrong. There is (practically) no way to guarantee this kind of timing. The application must rely on some kind of signalling to determine when data is ready, and in no way assume that data is available from multiple sources on a particular order.

Consider that, when the network is congested, then even a few incoming transactions from the host can drastically change the micro-timing of on-chip transaction travel. Same hold for DRAM data writebacks.

[shodruk]

[Gravis]