Parallella Community

The "Epiphany Architecture Reference Manual" mentions parallel scheduling of FPU and IALU instructions (around p.66).
May I therefore assume that parallel scheduling also holds for IALU and secondary IALU instructions?

Either way, further clarification inside applicable passages of the Reference Manual would be desirable, or is there any particular reason for why you treat the secondary IALU that poorly?
(I am especially referring to the Instruction Set Reference side of things, e.g. most, if not all, secondary IALU instructions seem to be lacking information on how and what flags are affected.)

edit: those flags might actually turn out to be a bit of a problem... If the secondary IALU flags are implemented analoguosly to the FPU flags, then we are missing a carry flag...

// edit 2
"The AV (integer overflow) flag set by the ADD instruction when the input signs are the same and the output sign is different from the input sign"
In a signed environment that would be:
negative + negative = positive -> underflow
positive + positive = negative -> underflow