Parallella Community

what does the Epiphany chip do when it's powered (it's initial state) and how does it boot up/load a program? does every core immediately execute a TRAP instruction and if so, how does it work?

Chip wakes in idle and awaits an interrupt. (bit [0] of the STATUS register is zero). Epiphany was designed as a coprocessor and does not boot by itself. At a minimum it needs an interrupt signal and a valid entry in the IVT location of the interrupt (0x0,0x4,etc..)

Andreas

Upon reset, the IVT vectors are reset to 0. At this time the Global Interrupt bit is enabled (GID == 0). The IRQ masks are also disabled (IMASK == 0) (*).

The IVT is initially populated by the host's loader. More precisely, the one vector that is always present is the SYNC vector, which is programmed with the start() function from the C runtime (CRT0). The "b 58 <.normal_start>" instruction is a part of your program's executable image. If you examine the "e-objdump -D" output, you'll see that at address 0. From there it becomes a record in the SREC image (you can view an SREC to verify that).

After loading the program (and populating IVT 0), a SYNC interrupt is required (done by e_start() from the host, or e_irq_set() from a neighbor core), and so the core branches to normal_start(), performs startup sequence and enters main().


(*) NOTE that while IMASK is rest to 0 at reset, in the CRT we decided to set its bits to "1" to mask the event interrupt - protecting against unwanted interrupts when using timers, DMA's, etc.