LDR/STR instructions

[Gravis]

do the LDR and/or STR instructions have to use addresses that are aligned to 32-bits or could you load/save the 16-bits in the middle of a 32-bit register? if it does have to be aligned, would it completely overwrite the entire 32-bits or just the 16-bits written to?

[ysapir]

The LDR/STR instructions can save a byte, a short (half-reg), a word (whole-reg) or a double-word (reg-pair). Depending on the <size> the address alignment can be 8-bit, 16-bit, 32-bit or 64-bit, resp.

The part of the register to load/save is always the least significant <size> bits.

[Gravis]

[aolofsson]

An illegal misaligned LDR/STR causes a software exception. (ie vector to IVT, address 0x4)

Andreas

[timpart]

A misaligned address also sets EXCAUSE to 010 in the status register (p47), since that interrupt can be used for several reasons (see table 21). Talking of which, what does EXCAUSE get set to for invalid instruction?

Tim