Parallella Community

Hi all

I would like to know the number of memory controllers between epiphany and dram.

According to my understanding, there is a fast interconnect between epiphany 2d mesh and main memory. If we go by this then there is one memory controller. However, this will become the bottleneck when having 4096 cores.

If we go by DMA engines, which are kind of virtual memory controllers, then it is one per Core.

Any help will really be appreciated.

Thanks
V Vanchinathan

Each eCore has one DMA engine with two channels.
Additionally, there is one eLink connection between the Epiphany mesh and the FPGA fabric.

I am not sure that counting "memory controllers" is useful.

Multiple memory controllers imply that we can have multiple parallel accesses from main memory. This is important as many cores will try to obtain data from main memory simultaneously.

Thanks

I disagree, but won't argue the point.

On the Parallella, there is only a single link between the FPGA and Epiphany chips. If used by many cores simultaneously, it will interleave accesses, which reduces the peak performance (no burst cycles).