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800MHz clock on Parallella board

https://parallella.org/forums/viewtopic.php?f=23&t=180

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800MHz clock on Parallella board

PostPosted: Sat Feb 16, 2013 8:35 am
by trioflex
Hi

can somebody explain how is 800MHz LVDS clock generated on Parallella.

Zynq PLL can not be used, at least according to Xilinx datasheet specifications.

r,
Antti

Re: 800MHz clock on Parallella board

PostPosted: Mon Feb 18, 2013 8:00 pm
by aolofsson
Antti,
We are still working on this part of the design. I hope to have some more detailed information regarding our solution this week. You are correct that based on the datasheet the Zynq cannot drive an LVDS pair up to 800MHz.
Andreas