800MHz clock on Parallella board

Any technical questions about the Epiphany chip and Parallella HW Platform.

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800MHz clock on Parallella board

Postby trioflex » Sat Feb 16, 2013 8:35 am

Hi

can somebody explain how is 800MHz LVDS clock generated on Parallella.

Zynq PLL can not be used, at least according to Xilinx datasheet specifications.

r,
Antti
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Re: 800MHz clock on Parallella board

Postby aolofsson » Mon Feb 18, 2013 8:00 pm

Antti,
We are still working on this part of the design. I hope to have some more detailed information regarding our solution this week. You are correct that based on the datasheet the Zynq cannot drive an LVDS pair up to 800MHz.
Andreas
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