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Parallella Community • View topic - Parallella 2.0 Design Specifications

Parallella 2.0 Design Specifications

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Re: Parallella 2.0 Design Specifications

Postby paran » Sat Jul 05, 2014 3:34 pm

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Re: Parallella 2.0 Design Specifications

Postby tnt » Sat Jul 05, 2014 6:22 pm

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Re: Parallella 2.0 Design Specifications

Postby paran » Sat Jul 05, 2014 7:21 pm

to tnt,
thanks for insights.
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Re: Parallella 2.0 Design Specifications

Postby Bikeman » Sat Jul 05, 2014 7:34 pm

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Re: Parallella 2.0 Design Specifications

Postby tnt » Sat Jul 05, 2014 8:02 pm

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Re: Parallella 2.0 Design Specifications

Postby Bikeman » Sat Jul 05, 2014 8:42 pm

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Re: Parallella 2.0 Design Specifications

Postby paran » Sat Jul 05, 2014 9:17 pm

I have raspberry pi too and I run it without a heat sink and have housing on it. So far no problem, however I use it occasionally(longest run was 3 hours non stop).
Zynq is not a cpu. it is actually FPGA with build in CPU. I could not find datasheet or other source of information about power rating. I found other FPGA equivalents from other companies (altera, actel) for comparison (it is not on fair footing because of specs diversity)

http://www.xilinx.com/products/silicon- ... /index.htm

1) http://www.wetech-ic.com/En/NewsView.asp?ID=79
2) http://www.microsemi.com/products/fpga- ... -cortex-m1

I still believe that 'cool cpu' can be found for parallella such as cell phone cpu.
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Re: Parallella 2.0 Design Specifications

Postby tnt » Sat Jul 05, 2014 10:52 pm

The Altera equivalent you posted is ... well equivalent, it won't have an especially better / worse power/speed ratio. The microsemi link is a ridiculously slow CPU implementation, probably 50x slower at least that the one in the Zynq.

You're right that the CPU in mobile phones are remarkably low power. Certainly a lot more than que Zynq ES we have, but a lot of this is also due to aggressive power management (shutting down or slowing down unused parts) and dedicated hw accelerators for the common tasks (like video playing which use very little the CPU).

But as stated above, you'll need a separate FPGA anyway for the epiphany interfacing which will eat your power gain of having a separate CPU, reduce the bandwidth between CPU and epiphany (and the external memory) and eat more board real-estate. So that doesn't seem like a viable idea.

As for the datasheet you can google for DS187, it will give you a lot of the numbers for the static consumption. But for the dynamic one, you need to go through the xilinx tools because, being heavily programmable, the FPGA power usage can vary dramatically depending on the way it's used.

But all in all, it's not that relevant. We know the whole board consumes 5W. Those 5W end up purely in heat and must be dissipated to the ambient air somehow and with such a small surface and a lot of it covered by component, it's definitely a challenge. For comparaison, a RPi is about 2.5W (and it's definitely more than twice slower !), so the energy efficiency of the board, even with the ES is really not bad, it just needs to reduce the theta-ja of the system to achieve passive cooling.
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Re: Parallella 2.0 Design Specifications

Postby xilman » Sun Jul 06, 2014 10:25 am

Here's my take. Not everyone will agree with me and some won't understand me because of a regretable tendency to be incoherent but here goes.

My personal interest is raw computation at lowest total system cost. I'm not particularly interested in the on-board presence of HDMI, USB, SD, PCIe and whatever per se nor in the absence of forced cooling. I want as many GIPS, GFLOPS, Gbytes and Gbps as I can get. I am entirely happy to off-load all the heavy lifting of OS, storage, internet connectivity, user interface, dev-tools, etc on to regular PCs which, after all, is what they are good at.

So desiderata include as full as possible mesh interconnectivity between Epiphany processors on different boards; memory bandwidth as high as possible; memory size as high as possible; system clock frequency as high as possible. Dual GbE connectors per board would be nice.

Long term, I'd like to see a full-length PCIe card filled with wall-to-wall Zynq & Epiphany chips, especially so if they support 64-bit arithmetic. A real supercomputer on a card, IOW. I'm fully aware that these would cost real money.
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Re: Parallella 2.0 Design Specifications

Postby paran » Mon Jul 07, 2014 3:10 am

To xilman,
I understood you. It is a good suggestion. However, I see nothing wrong with embedded approach. Besides, adapteva can do both approaches, the embedded one and the one you suggested which is add on to pc.
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