Re: FPGA Source / Project Repository
Posted: Thu Jul 03, 2014 11:22 pmI will try it tomorrow, really appreciated it.
Thanks a lot, Frank =)
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FPGA Source / Project Repository
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Posted: Thu Jul 03, 2014 11:22 pmRe: FPGA Source / Project Repository
Posted: Fri Jul 04, 2014 4:42 amRe: FPGA Source / Project Repository
Posted: Sat Oct 11, 2014 8:45 pmHi Fred,
I've found some bugs in the parallella-hw project.
In parallella_7020_hdmi:
XPS > Clock Generation > PL Fabric Clocks > FCLK_CLK1 is set to 152.
I changed it to 125.
In parallella_7010_hdmi, parallella_7020_hdmi:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 (changed to 100000000)
CLKOUT0: Required Frequency: 0 (changed to 12288135)
After changing these parameters, I generated the bitstream, and I've got HDMI sound working!! Yay!!
(I tested with parallella_7020_hdmi.)
I've found some bugs in the parallella-hw project.
In parallella_7020_hdmi:
XPS > Clock Generation > PL Fabric Clocks > FCLK_CLK1 is set to 152.
I changed it to 125.
In parallella_7010_hdmi, parallella_7020_hdmi:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 (changed to 100000000)
CLKOUT0: Required Frequency: 0 (changed to 12288135)
After changing these parameters, I generated the bitstream, and I've got HDMI sound working!! Yay!!
(I tested with parallella_7020_hdmi.)
Re: FPGA Source / Project Repository
Posted: Wed Oct 15, 2014 7:37 pmRe: FPGA Source / Project Repository
Posted: Sun Oct 19, 2014 7:41 pmSuper catch.
How do we get these changes in the current build?
How do we get these changes in the current build?
Re: FPGA Source / Project Repository
Posted: Mon Oct 20, 2014 3:08 amHi Shodruky / Len,
Sorry I haven't had a chance to look this over before now, too many first-priorities! The 7010 problem is very puzzling because I have built and used that code and project as-is on hardware, I don't see any changes to the repository. The audio issue is puzzling too but somehow I must have been using the old (pre-"me") bitstreams when I had audio working and only noticed the problem after we updated the kernel and lots of other things. I'll check that out too.
I'll be sure to go over these items in detail early this week and update the repository to incorporate the fixes.
Thanks for the detective work Shodruky!
Sorry I haven't had a chance to look this over before now, too many first-priorities! The 7010 problem is very puzzling because I have built and used that code and project as-is on hardware, I don't see any changes to the repository. The audio issue is puzzling too but somehow I must have been using the old (pre-"me") bitstreams when I had audio working and only noticed the problem after we updated the kernel and lots of other things. I'll check that out too.
I'll be sure to go over these items in detail early this week and update the repository to incorporate the fixes.
Thanks for the detective work Shodruky!
Re: FPGA Source / Project Repository
Posted: Mon Oct 20, 2014 1:34 pmThanks Fred,
I'm using kernel-hdmi-140603.tgz (not the latest one on the linux kernel repository)
I'm using kernel-hdmi-140603.tgz (not the latest one on the linux kernel repository)
Re: FPGA Source / Project Repository
Posted: Wed Oct 22, 2014 4:09 amRe: FPGA Source / Project Repository
Posted: Wed Oct 22, 2014 11:41 amRe: FPGA Source / Project Repository
Posted: Thu Oct 23, 2014 12:34 amThanks Fred, I understand.
The CLK1_FREQ issue is due to ISE.
I restored the CLK1 setting (to 152), generated bitstream, it succeeded.
I found my 40Mhz clock hack is not reliable, some monitors worked, but some didn't.
I tried the PLL mode of the clock_generator_0, it works fine!
Also I generated the 7010 bitstream and it completed successfully!
Summary of the Modification:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 -> 100000000
CLKOUT0 > Required Frequency: 0 -> 12288135
CLKOUT0 > Required Group: None -> PLLE0
".asoundrc" is still necessary.
Please ignore other modifications.
The CLK1_FREQ issue is due to ISE.
I restored the CLK1 setting (to 152), generated bitstream, it succeeded.
I found my 40Mhz clock hack is not reliable, some monitors worked, but some didn't.
I tried the PLL mode of the clock_generator_0, it works fine!
Also I generated the 7010 bitstream and it completed successfully!
Summary of the Modification:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 -> 100000000
CLKOUT0 > Required Frequency: 0 -> 12288135
CLKOUT0 > Required Group: None -> PLLE0
".asoundrc" is still necessary.
Please ignore other modifications.