Hi,
I was installing Vivado (the latest Xilinx design tools) on my Fedora 18/64 system today, with as the purpose to recompile some stuff I want to try out on both my Spartan 3e board and (once it gets there) the Parallella, and to try out running the "standard design" for the Parallella FPGA, to make my own bit files.
I couldn't find the pin count (nor strictly speaking the speed variation, but I presume it's -1 like the Zinq 7020), and also not a "top" module for the 7010 variation, and strangely enough also not a single picture I could find that states the exact chip number!
Is there some way currently to get the up to date, working actual design that's in the current 7010 based Parallella boards in verilog form, and some sort of guide where the stub-files go, because just loading in the 7020 .v . udf and .xc files from Git didn't look very good, is there a complete project zip for instance ? I presume one has been made, considering there are working 7010 boards on the markets, in the spirit of the OS it shouldn't be too hard to zip the used project.
I'll have to download ISE 14.7 tomorrow, too, and check out my Spartan 3e design, so maybe I'll have another look, but either I've been using the wrong files, or I'm missin gsomething here.
T.