eLink bandwidth

[Gravis]

the reads that there is "8 GB/s Off-Chip Bandwidth" and i was wonder if this was referring to one eLink, all the eLinks combined, or something else. also, is this the total bandwidth for RX and TX running simultaneously. if it's total for all eLinks and simultaneous RX/TX then i calculate it would be 1GB/s TX and 1GB/s RX per eLink.

[fdeutschmann]

As I pointed out in the other thread , per the datashhet (the lart that matters: the tech part), the bandwidth of the off-chip eLink is:

The E16G301 chip has 4 bi-directional (full-duplex) NEWS links, and each link runs at a speed derived by a divided version of the eCore clock; the divisor is 2, 4, or 8. The external eLink itself is 8 bits wide, with a bit clock, a frame clock, and 2x flow control sigs: 24 signal diff pairs per NEWS eLink. With the current part running at full spec of 700 MHz, seems to me the eLink can transfer at most ~333 MB / sec in each direction, but there is some overhead required for sending the transaction wrapper data: address, etc. Across all NEWS eLinks, this aggregates to ~1.3 GB/s inbound and outbound simultaneously, assuming no congestion. Which is very, very good - but a lot less than what is quoted: please correct me if I'm wrong.....

For the next generation part with an eCore clock spec limit of 1Ghz, eLink bandwidth would correspondingly increase to approx 476 MB/sec full duplex per NEWS link, minus transaction overhead: approx 1.8 GB/s simultaneously inbound and outbound (full duplex) across all 4 NEWS links.

Note that running the eLink at even 350 MHz (the current spec limit) will require a very well designed and implemented PCB; keeping the 12 signals of each duplex in sufficient alignment at this speed requires great attention to detail! (I hope the next gen of the chip provides a DDR mode for the eLink; seems as the internal eLink is running at full eCore speed that should be do-able. But I'd also like to see more memory per eCore and double precision and and and....)

Each of the NEWS eLinks requires 48 pins for the bidirectional full duplex link; it does not seem to be permissible to implement only one of the directions.


In response to your other question on that thread: ethernet is spec'ed as full or half duplex at the option of the implementation, negotiated at link init. But I have yet to see a half duplex 10GbE implemention. With current state of the art eqiupment that is properly tuned, I have seen a max of about 70% capacity utilization with packets averaging ~600 B.

-frank

[timpart]

My understanding of the peak bandwidth quoted is that is for a continuous stream of double words (8 bytes) at a time. The eLink doesn't send out address data if the double words are to consecutive locations. Andres comments that if if the data stream requires addresses to be sent too then performance is about a third of peak.

I think the 8 gigabytes per second is based on a 1 gigahertz clock and all four links doing bidirectional operation with consecutive double words.

Tim

[Gravis]

[shodruk]

Bus bandwidth != Data bandwidth

The eLink BUS bandwidth is 8GB/s on 1GHz clock. (4 links, TX, RX, data, address, total)
The eLink bus packet contains 32bit data, 32bit src address, 32bit dst address, frames, flags, etc...
And, a read operation consumes not only RX bandwidth, but also TX bandwidth.
(First Epiphany sends a read request packet (32bit src address, 32bit dst address, flags...) to Zynq, then Zynq sends back data+dst address to Epiphany.)
So, basically we cannot get 8GB/s data bandwidth.

[Gravis]