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Parallella Community • View topic - Epiphany memory architecture

Epiphany memory architecture

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Epiphany memory architecture

Postby Amir » Tue Nov 12, 2013 2:40 pm

Hello :)

There is something that I am not getting, I need help please. I read that the parallella computer has 1 GB RAM. And as far as I understood, each epiphany eCore has its own local memory that is divided into 4 parts, each part being 8 bytes wide so it makes the total local memory 32 Bytes. So, does it mean that each eCore has 32 Bytes of internal memory? And also, does this internal memory add on to 1 GB RAM? Or is it a part of it? :s

I also want to ask that is that 1 GB memory shared by the epiphany eCores? If yes then what's the purpose of internal memory?

I really need help on this please.
Amir
 
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Re: Epiphany memory architecture

Postby 9600 » Tue Nov 12, 2013 3:11 pm

Each core has 32KB of local memory and it can access this faster than it can the memory local to another core, and a great deal faster than it can off-chip memory. So this is where you want to put Epiphany programs and ideally the data they work on.

Cheers,

Andrew
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Re: Epiphany memory architecture

Postby Amir » Tue Nov 12, 2013 3:17 pm

Thanks... it made it a lot clear to me :)

But, in the manual I read that each eCore's local memory has 32 Bytes. So howcome 32 KB? it might be a silly question but I am not getting it so I need help please :)
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Re: Epiphany memory architecture

Postby 9600 » Tue Nov 12, 2013 3:27 pm

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Re: Epiphany memory architecture

Postby Amir » Tue Nov 12, 2013 3:35 pm

Oh right! I got it.

One more question plz:

The Epiphany architecture uses a single, flat address space consisting of 2^32 8-bit bytes. Byte addresses are treated as unsigned numbers, running from 0 to 2^32– 1. This address space is regarded as consisting of 2^30 32-bit words, each of whose addresses is word-aligned, which means that the address is divisible by 4. The word whose word-aligned address is A consists of
the four bytes with addresses A, A+1, A+2 and A+3. Each mesh node has a local, aliased, range of memory that is accessible by the mesh node itself starting at address 0x0 and ending at address 0x00007FFF.

Can u please just explain me what it all says? I'm having difficulty in understanding this.
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Re: Epiphany memory architecture

Postby 9600 » Tue Nov 12, 2013 3:55 pm

This introductory may help.
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Re: Epiphany memory architecture

Postby Amir » Tue Nov 12, 2013 4:03 pm

Thanks a lot! :)
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