Parallella Community

Announcements	Statistics	Last post
	Zynq docoumentation by aolofsson » Thu Apr 17, 2014 3:26 pm	Replies: 0 Views: 48461	Thu Apr 17, 2014 3:26 pm by aolofsson

Statistics	Last post
Splicing messages over the Epiphany FPGA connection by theover » Fri Feb 13, 2015 9:30 pm	Replies: 0 Views: 8254	Fri Feb 13, 2015 9:30 pm by theover
JTAG POWER_PEC + Vivado Question 1, 2 by Michael19 » Mon Sep 15, 2014 3:52 pm	Replies: 13 Views: 43907	Fri Jan 09, 2015 5:42 am by shankar
Jtag support by steddyman » Mon Dec 29, 2014 5:47 pm	Replies: 4 Views: 17357	Mon Dec 29, 2014 8:07 pm by steddyman
External text editor from planAhead by shaskey » Thu Dec 11, 2014 10:38 pm	Replies: 0 Views: 8527	Thu Dec 11, 2014 10:38 pm by shaskey
2 Questions by theover » Mon Nov 10, 2014 8:16 pm	Replies: 0 Views: 8410	Mon Nov 10, 2014 8:16 pm by theover
Porting FuseSOC to the Parallella by yanidubin » Sat Oct 04, 2014 12:32 pm	Replies: 7 Views: 27905	Sun Oct 19, 2014 4:53 pm by Len
TFT display by patc » Sun Oct 12, 2014 4:17 pm	Replies: 1 Views: 10483	Wed Oct 15, 2014 7:33 pm by aolofsson
Is the Parallella a good platform for learning about FPGAs? by jacob12 » Sat Oct 04, 2014 3:56 am	Replies: 1 Views: 10292	Sat Oct 04, 2014 5:09 am by FHuettig
openPOWERLINK on Parallella by pedro_nf » Fri Jun 27, 2014 1:45 pm	Replies: 1 Views: 11745	Thu Oct 02, 2014 10:33 am by yanidubin
system_stub.v confusion by AndyC » Wed Sep 24, 2014 10:42 am	Replies: 6 Views: 21844	Tue Sep 30, 2014 5:43 am by AndyC
FPGA 101? 1, 2 by the_summer » Fri Jul 05, 2013 5:44 am	Replies: 15 Views: 53336	Fri Sep 26, 2014 7:45 am by yanidubin
FPGA Partial Reconfiguration by yanidubin » Thu Sep 25, 2014 9:40 am	Replies: 1 Views: 11684	Thu Sep 25, 2014 10:00 am by yanidubin
FPGA Multiplexing for daughter boards by yanidubin » Tue Sep 23, 2014 8:44 am	Replies: 4 Views: 19718	Thu Sep 25, 2014 9:41 am by yanidubin
AXI Peripheral. Works in hdmi project but not in headless 1, 2, 3 by AndyC » Mon Sep 22, 2014 12:08 pm	Replies: 22 Views: 69788	Wed Sep 24, 2014 10:15 am by 9600
promgen: An easier way to generate .bit.bin by yanidubin » Tue Sep 23, 2014 9:46 am	Replies: 2 Views: 13493	Tue Sep 23, 2014 11:51 pm by yanidubin
Routing additional Zynq hard block I/O to PEC_FPGA 1, 2 by 9600 » Sun May 04, 2014 11:17 am	Replies: 12 Views: 54865	Tue Sep 23, 2014 8:46 am by yanidubin
ARM FPGA communication 1, 2 by theover » Tue Sep 09, 2014 12:55 am	Replies: 16 Views: 52820	Tue Sep 23, 2014 8:13 am by yanidubin
parallella-hw fpga project structure - why? by yanidubin » Sun Sep 21, 2014 5:24 am	Replies: 4 Views: 18208	Tue Sep 23, 2014 8:06 am by yanidubin
/dev/xdevcfg - How to get working? by AndyC » Fri Sep 19, 2014 3:57 pm	Replies: 1 Views: 10312	Fri Sep 19, 2014 4:08 pm by AndyC
Disable Elink in FPGA [solved] by moses_rotesmeer » Mon Sep 15, 2014 6:16 pm	Replies: 2 Views: 10277	Thu Sep 18, 2014 11:41 pm by moses_rotesmeer
Error synthesising by AndyC » Thu Sep 11, 2014 10:27 am	Replies: 5 Views: 18026	Thu Sep 18, 2014 8:47 pm by FHuettig
PL RTC substitute by zmc » Mon Sep 01, 2014 4:41 pm	Replies: 1 Views: 9015	Mon Sep 01, 2014 6:13 pm by 9600
Zynq Errata by aolofsson » Mon Aug 18, 2014 11:17 am	Replies: 1 Views: 8926	Mon Aug 18, 2014 11:51 am by ajtravis
An open source GPU for Parallella by aolofsson » Sun Aug 03, 2014 6:14 pm	Replies: 3 Views: 13391	Wed Aug 06, 2014 12:12 am by asicguy
a 64 channel logic analyzer with 100 MHz samplerate by frank_buss » Thu Jul 31, 2014 10:20 am	Replies: 6 Views: 26518	Mon Aug 04, 2014 2:09 pm by aolofsson

Topics

Statistics

Last post

Splicing messages over the Epiphany FPGA connection

by theover » Fri Feb 13, 2015 9:30 pm

Replies: 0

Views: 8254

Fri Feb 13, 2015 9:30 pm

by theover

JTAG POWER_PEC + Vivado Question

1, 2

by Michael19 » Mon Sep 15, 2014 3:52 pm

Replies: 13

Views: 43907

Fri Jan 09, 2015 5:42 am

by shankar

Jtag support

by steddyman » Mon Dec 29, 2014 5:47 pm

Replies: 4

Views: 17357

Mon Dec 29, 2014 8:07 pm

by steddyman

External text editor from planAhead

by shaskey » Thu Dec 11, 2014 10:38 pm

Replies: 0

Views: 8527

Thu Dec 11, 2014 10:38 pm

by shaskey

2 Questions

by theover » Mon Nov 10, 2014 8:16 pm

Replies: 0

Views: 8410

Mon Nov 10, 2014 8:16 pm

by theover

Porting FuseSOC to the Parallella

by yanidubin » Sat Oct 04, 2014 12:32 pm

Replies: 7

Views: 27905

Sun Oct 19, 2014 4:53 pm

by Len

TFT display

by patc » Sun Oct 12, 2014 4:17 pm

Replies: 1

Views: 10483

Wed Oct 15, 2014 7:33 pm

by aolofsson

Is the Parallella a good platform for learning about FPGAs?

by jacob12 » Sat Oct 04, 2014 3:56 am

Replies: 1

Views: 10292

Sat Oct 04, 2014 5:09 am

by FHuettig

openPOWERLINK on Parallella

by pedro_nf » Fri Jun 27, 2014 1:45 pm

Replies: 1

Views: 11745

Thu Oct 02, 2014 10:33 am

by yanidubin

system_stub.v confusion

by AndyC » Wed Sep 24, 2014 10:42 am

Replies: 6

Views: 21844

Tue Sep 30, 2014 5:43 am

by AndyC

FPGA 101?

1, 2

by the_summer » Fri Jul 05, 2013 5:44 am

Replies: 15

Views: 53336

Fri Sep 26, 2014 7:45 am

by yanidubin

FPGA Partial Reconfiguration

by yanidubin » Thu Sep 25, 2014 9:40 am

Replies: 1

Views: 11684

Thu Sep 25, 2014 10:00 am

by yanidubin

FPGA Multiplexing for daughter boards

by yanidubin » Tue Sep 23, 2014 8:44 am

Replies: 4

Views: 19718

Thu Sep 25, 2014 9:41 am

by yanidubin

AXI Peripheral. Works in hdmi project but not in headless

1, 2, 3

by AndyC » Mon Sep 22, 2014 12:08 pm

Replies: 22

Views: 69788

Wed Sep 24, 2014 10:15 am

by 9600

promgen: An easier way to generate .bit.bin

by yanidubin » Tue Sep 23, 2014 9:46 am

Replies: 2

Views: 13493

Tue Sep 23, 2014 11:51 pm

by yanidubin

Routing additional Zynq hard block I/O to PEC_FPGA

1, 2

by 9600 » Sun May 04, 2014 11:17 am

Replies: 12

Views: 54865

Tue Sep 23, 2014 8:46 am

by yanidubin

ARM FPGA communication

1, 2

by theover » Tue Sep 09, 2014 12:55 am

Replies: 16

Views: 52820

Tue Sep 23, 2014 8:13 am

by yanidubin

parallella-hw fpga project structure - why?

by yanidubin » Sun Sep 21, 2014 5:24 am

Replies: 4

Views: 18208

Tue Sep 23, 2014 8:06 am

by yanidubin

/dev/xdevcfg - How to get working?

by AndyC » Fri Sep 19, 2014 3:57 pm

Replies: 1

Views: 10312

Fri Sep 19, 2014 4:08 pm

by AndyC

Disable Elink in FPGA [solved]

by moses_rotesmeer » Mon Sep 15, 2014 6:16 pm

Replies: 2

Views: 10277

Thu Sep 18, 2014 11:41 pm

by moses_rotesmeer

Error synthesising

by AndyC » Thu Sep 11, 2014 10:27 am

Replies: 5

Views: 18026

Thu Sep 18, 2014 8:47 pm

by FHuettig

PL RTC substitute

by zmc » Mon Sep 01, 2014 4:41 pm

Replies: 1

Views: 9015

Mon Sep 01, 2014 6:13 pm

by 9600

Zynq Errata

by aolofsson » Mon Aug 18, 2014 11:17 am

Replies: 1

Views: 8926

Mon Aug 18, 2014 11:51 am

by ajtravis

An open source GPU for Parallella

by aolofsson » Sun Aug 03, 2014 6:14 pm

Replies: 3

Views: 13391

Wed Aug 06, 2014 12:12 am

by asicguy

a 64 channel logic analyzer with 100 MHz samplerate

by frank_buss » Thu Jul 31, 2014 10:20 am

Replies: 6

Views: 26518

Mon Aug 04, 2014 2:09 pm

by aolofsson

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

FPGA Design

Zynq docoumentation

Splicing messages over the Epiphany FPGA connection

JTAG POWER_PEC + Vivado Question

Jtag support

External text editor from planAhead

2 Questions

Porting FuseSOC to the Parallella

TFT display

Is the Parallella a good platform for learning about FPGAs?

openPOWERLINK on Parallella

system_stub.v confusion

FPGA 101?

FPGA Partial Reconfiguration

FPGA Multiplexing for daughter boards

AXI Peripheral. Works in hdmi project but not in headless

promgen: An easier way to generate .bit.bin

Routing additional Zynq hard block I/O to PEC_FPGA

ARM FPGA communication

parallella-hw fpga project structure - why?

/dev/xdevcfg - How to get working?

Disable Elink in FPGA [solved]

Error synthesising

PL RTC substitute

Zynq Errata

An open source GPU for Parallella

a 64 channel logic analyzer with 100 MHz samplerate

Who is online

Forum permissions