Missing FPGA stuff

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Missing FPGA stuff

Postby rec » Mon May 05, 2014 6:39 pm

Just a n00b here, bumbling my way through an FPGA design to see if I can embarrass someone better prepared to take it over from me. I've gotten the ISE Webpack 14.7 installed and licensed. I've been ferreting out what I can find in the documentation. But still I'm puzzled about a few things:

1) Where is the source for the HDMI interface? I've seen the vague pointers to and hand waving at Analog Devices pages which cover multiple reference designs none of which are clearly identified as suitable for the ADV7513 or for the Parallella. There must be a source for the bitstream that you're delivering to us, no? Where is it? How much of the FPGA does it use? How much power is it consuming? How do we rebuild it with modifications?

2) How is the parallella.bit.bin file on the boot partition created? It is not the bitstream format produced by the Xilinx tools used to produce parallella-hw/fpga/bitstreams/*.bit, it's been processed into another format. What is the format? How is the processing done? Can another bitstream be substituted into its place by simply copying the processed bitstream file onto the boot partition? Or is there some more complicated process like parallella-hw/boards/parallella-I/firmware/README?

3) How is the FPGA configuration managed after system boot? There is code in the uboot source to DMA the bootstrap bitstream into the configuration RAM during boot. That's fine if you're running on bare hardware. The Xilinx documents claim that it is possible to read and to write the configuration RAM at any time. What are the tools for doing this? How do I install the bitstream parallella_e16_headless_nogpio_7020.bit to test if it works? Has anyone tested it?

I'm sure there will be more questions in time, but those are the ones that prevent me from recreating parallella-hw/fpga/bitstreams/parallella_e16_headless_nogpio_7020.bit from sources and testing my build process.

-- rec --

[edited to fix the ADV7513 part number]
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Re: Missing FPGA stuff

Postby FHuettig » Mon May 05, 2014 9:53 pm

HI rec,

rec wrote:1) Where is the source for the HDMI interface? I've seen the vague pointers to and hand waving at Analog Devices pages which cover multiple reference designs none of which are clearly identified as suitable for the ADV7513 or for the Parallella. There must be a source for the bitstream that you're delivering to us, no? Where is it? How much of the FPGA does it use? How much power is it consuming? How do we rebuild it with modifications?


Yeah, sorry about that, I haven't had a chance to get the HDMI-enabled version of the source tested & released yet. It relies on a small part of a large github repository from ADI. I should be doing that this week, in the mean time I recommend you get started with the headless version. If you look at the top-level verilog code you'll see that the HDMI signals come from a wrapper produced by the EDK (XPS), and the same top-level uses `define's to deal with the HDMI signals for either version. So if your project doesn't require modification to the PS wrapper you won't have to worry about it, there won't be any conflicts. If you do need to change the PS interface you'll have some merging to do, but it shouldn't be too much.

The HDMI logic increases the total power consumption by 0.75~1.0W, I can't tell you how much of the device it uses.

rec wrote:2) How is the parallella.bit.bin file on the boot partition created? It is not the bitstream format produced by the Xilinx tools used to produce parallella-hw/fpga/bitstreams/*.bit, it's been processed into another format. What is the format? How is the processing done? Can another bitstream be substituted into its place by simply copying the processed bitstream file onto the boot partition? Or is there some more complicated process like parallella-hw/boards/parallella-I/firmware/README?


As you saw in the firmware/README, you have to use the Xilinx tool "bootgen" to convert the .bit file into a raw binary .bin file. I think the only difference is that the .bit has a header on it, and maybe the bit order is different, I haven't looked in a long time. The instructions in the README are for creating the boot image that goes into the onboard flash, I would leave that alone unless you need to change the FSBL (say to change the MIO configuration). To create a file that you can use to replace the default parallella.bit.bin you have to use the -split bin option with bootgen. Start with the existing files, either rename your bitstream to the one named in the bif file or change the name in the bif file, and run (I'm using linux, YMMV):

Code: Select all
. /opt/Xilinx/14.7/ISE_DS/settings64.sh
bootgen -image bootimage.bif -split bin


rename the resulting .bit.bin file to parallella.bit.bin (after saving the original just in case!) and you should be good to go.

rec wrote:3) How is the FPGA configuration managed after system boot? There is code in the uboot source to DMA the bootstrap bitstream into the configuration RAM during boot. That's fine if you're running on bare hardware. The Xilinx documents claim that it is possible to read and to write the configuration RAM at any time. What are the tools for doing this?

The system first loads a bitstream from flash during the FSBL (first-stage boot-loader), and then u-boot reconfigures with parallella.bit.bin from the SD card. After that we normally don't reconfigure again, but it should be possible using xdevcfg (I have not tried it):
http://forums.xilinx.com/t5/Embedded-Linux/Zynq-Loading-bitfile-into-FPGA-from-Linux-xdevcfg/td-p/237850

Or, if you don't load the linux image you should be able to use the fpga command from u-boot (again, I haven't tried it).

rec wrote:How do I install the bitstream parallella_e16_headless_nogpio_7020.bit to test if it works? Has anyone tested it?

I install it as above, and I try it nearly every day! :)

rec wrote:I'm sure there will be more questions in time, but those are the ones that prevent me from recreating parallella-hw/fpga/bitstreams/parallella_e16_headless_nogpio_7020.bit from sources and testing my build process.

Note that the latest version adds single-ended GPIOs connected to the arms, and reduces the power consumption in the process. parallella_e16_headless_gpiose_7002.bit

Cheers,
Fred
-- Fred -- Hardware Guy --
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Re: Missing FPGA stuff

Postby rec » Mon May 05, 2014 10:17 pm

Thanks Fred --

That should keep me busy for a few days.

-- rec --
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Re: Missing FPGA stuff

Postby rec » Mon May 05, 2014 11:25 pm

A few lessons on reprogramming the fpga from the command line.

The major device number of /dev/xdevcfg is different on the parallella than in earlier boards and the path to the prog_done register has also changed a bit.
Code: Select all
sudo mknod /dev/xdevcfg c 250 0

creates the node correctly, the major device number is 250 instead of 259, and
Code: Select all
sudo -s
cat parallella.bit.bin > /dev/xdevcfg
exit

reprograms the fpga with the same bits it used at boot. You need to be root before you type the command because the device can only be written by root.
Code: Select all
cat /sys/devices/amba.1/f8007000.devcfg/prog_done

will find 1 if the program took. (On earlier boards it was an amba.0 device.)

As a bonus, the /dev/xdevcfg driver now recognizes plain bit files, so there is no need to run bootgen.
Code: Select all
sudo -s
cat parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
exit

reprograms the fpga to be headless with normal gpio mappings. The only evidence that the right thing is done appears in /var/log/syslog where the driver reports whether the syncword was normal or swapped.

Do not try to read from /dev/xdevcfg, the read will time out, every subsequent operation on the device will also time out, and prog_done will report 0. You will need to reboot to regain control of the FPGA.

Code: Select all
ls /sys/devices/amba.1/f8007000.devcfg

will show you some other registers you can mess with in this interface.

-- rec --
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Re: Missing FPGA stuff

Postby FHuettig » Tue May 06, 2014 3:27 am

Awesome! Thanks for the info, rec. I've been meaning to look into that process for weeks. -Fred
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Re: Missing FPGA stuff

Postby theover » Tue May 06, 2014 1:55 pm

Apart from some corrections I think most of the mentioned answer components were already mentioned in the past.

My question is: do you get easily from the FPGA verilog to the bit file with the ISE tools, and a good working connections with the ARM CPU (like in other projects such as the Zedboard has been discussed quite a while ago), to begin with ?

T.
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Re: Missing FPGA stuff

Postby FHuettig » Tue May 06, 2014 2:42 pm

theover wrote:Apart from some corrections I think most of the mentioned answer components were already mentioned in the past.


I'm sure I've missed a lot, I've only been involved for a couple of months. but it's nice to have all corrections in one place.

T, I'm not sure I understand your question:

theover wrote:My question is: do you get easily from the FPGA verilog to the bit file with the ISE tools,


If you pull the parallella-hw repository, open one of the PlanAhead projects, and click on "Generate Bitstream" it should build without problems. I've been doing all my builds under Ubuntu Linux 64b, so if there are problems building under other environments I'll want to hear about it.

theover wrote:and a good working connections with the ARM CPU (like in other projects such as the Zedboard has been discussed quite a while ago), to begin with ?


All our tests pass with the generated bitstreams, the connections from the ARMs to the Epiphany are solid, that's the only thing in the (headless) bitstream currently besides passing the GPIOs through. Are there particular problems you are referring to?

-Fred
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Re: Missing FPGA stuff

Postby rec » Tue May 06, 2014 3:25 pm

It's easy for some values of easy.

I installed ISE Webpack on an i7 laptop running Ubuntu 14.04. The only mods to Ubuntu were to: 1) change /bin/sh into a symbolic link to /bin/bash; and 2) add a symbolic link for /usr/bin/gmake to /usr/bin/make. These are the Fedora/Ubuntu inconsistencies that have been noted elsewhere. I pulled a license file manually from the xilinx website and stored it in ~/.Xilinx/.

I ran planAhead on Fred's parallella-hw/fpga/projects/parallella_7020_headless/ project. According to the 34 Mbytes of logs and outputs produced, it took 8 minutes to generate the bit file. I may have slowed things down by not responding to some alerts as fast as possible.

The output file differs from Fred's bitstreams/parallella_e16_headless_gpiose_7020.bit at 7 bytes between positions 88 and 103.
Code: Select all
od -c -A d impl_1/parallella_z7_top.bit | head
shows an ascii date and time at that location in the file.

good working connections with the ARM CPU (like in other projects such as the Zedboard has been discussed quite a while ago), to begin with ?


No idea what you're asking about here.

Ah, tried reprogramming the FPGA 10 times in a for loop. The first 3 succeeded, the last 7 failed with the error "cat: write error: Cannot allocate memory" and the FPGA prog_done register is now 0.

Rebooted and tried the loop of 10 writes again. The first 4 succeed, the last 6 failed. The messages in the syslog are:
Code: Select all
May  6 09:15:14 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: last message repeated 4 times
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:16 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:16 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:16 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:16 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:16 linaro-nano kernel: Found swapped sync word
May  6 09:15:16 linaro-nano kernel: Did not transfer last 3 bytes
May  6 09:15:17 linaro-nano kernel: xi2cps e0004000.i2c: timeout waiting on completion
May  6 09:15:50 linaro-nano kernel: last message repeated 3 times


-- rec --
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Re: Missing FPGA stuff

Postby rec » Thu May 15, 2014 4:39 pm

So, this seems like a pretty embarrassing bug for Xilinx, or whoever is responsible for this driver. It only requires 5 shell commands to demonstrate.

Code: Select all
$ cat bitstreams/parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
$ cat bitstreams/parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
$ cat bitstreams/parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
$ cat bitstreams/parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
$ cat bitstreams/parallella_e16_headless_gpiose_7020.bit > /dev/xdevcfg
cat: write error: Cannot allocate memory


Anyone who can deliver a Linux device driver without writing the shell command loop that verifies the driver works more than 4 times after a boot is really making a definitive statement about their quality control procedures.

I've written a tcl script that reproduces the same error as cat while buffering the whole bitstream into one write.

I tried to write a C program to exercise the devcfg interface directly, hoping to get more clues about what is failing, but there are no system headers installed on the quick start image. And though there is a linux-headers package in the repos installed on the quick start image, they refer to a linux-image package which is not the source of the linux on the quick start image.

You guys should sort that out. Either build proper linux-image and linux-headers .deb packages, maintain a repo to distribute them, or block the wrong ones from being installed by accident. As it's set up, I suspect it's an open invitation to brick your sd card. Building a .deb package to distribute the edk shouldn't be too much work for your contractors, either.

Meanwhile, how do we get this bug in the /dev/xdevcfg driver sorted out?

-- rec --
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Re: Missing FPGA stuff

Postby frank_buss » Thu Jun 19, 2014 9:35 am

rec wrote:1) Where is the source for the HDMI interface? I've seen the vague pointers to and hand waving at Analog Devices pages which cover multiple reference designs none of which are clearly identified as suitable for the ADV7513 or for the Parallella. There must be a source for the bitstream that you're delivering to us, no? Where is it? How much of the FPGA does it use? How much power is it consuming? How do we rebuild it with modifications?

The HDMI projects are now working. As mentioned in another thread, it is all explained in "fpga\projects\parallella_7020_hdmi\README.md".

Note: on Windows the script get_fpgahdl_xilinx works best with Cygwin, after changing the newlines to Unix format. On my system the script ends with an error "error: Entry 'cf_ad9361_ml605/SDK/SDK_Export/hw/system.bit' not uptodate. Cannot update sparse checkout.", but looks like you can ignore it. The source code for the HDMI module is in fpga\externals\fpgahdl_xilinx\cf_lib\edk\pcores\axi_hdmi_tx_v1_00_a\hdl\verilog after running the script.

When trying to generate the bitstream in PlanAhead, I get 3 critical warnings, as explained in https://github.com/parallella/parallell ... 0_headless , which can be ignored. The bitstream file name is "fpga\projects\parallella_7020_hdmi\parallella_7020_hdmi.runs\impl_1\parallella_z7_top.bit". The getbits-script doesn't work on Windows, but you can start a "ISE Design Suite 64 Bit Command Prompt" and start "bootgen -image bit2bin.bif -split bin" from the "fpga\projects\parallella_7020_hdmi" directory. It creates a "parallella_z7_top.bit.bin" file, which you can copy as "parallella.bit.bin" to the sd-card.

Only 13% of the LUTs are used, now I can start implementing some interesting stuff 8-)
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