Hi,
Here's a list of what I'd like to see happen :
* Better encapsulation
By this I mean both refrain to use too generic names. I mean 'axi_master' is a pretty generic name for something that's completely specific to the eLink. I think something like emesh_axi_master or elink_axi_master would be more appropriate.
I also mean that the whole AXI <-> eMesh should be a module in itself, something pretty self contained that can be copied to another project. Currently you have to copy several subdirs and correctly interconnect them. Or maybe that's what parallella.v is supposed to be ? But then I would still comment that the name isn't great (because it's just the elink part and not the whole parallella design) and I'd make sure the directory reflects that (i.e. don't have the parallella_z7_top.v top level in the same dir).
Something like :
hdl/
top/
parallella_z7_top.v
elink/
elink_top.v
axi/...
phy/...
utils/...
So that you can easily just copy elink/ to your own project, wire the two AXI to the PS7 and the other wires to the pads and you get a working elink in your project.
This could even be a submodule with it's own vivado tcl script to set-it up so that updates are easier.
* Improved compatibility with the Rev 0 board.
Using generic (or whatever the verilog equivalent is), it should be fairly straight forward to have this AXI <-> eMesh wrapper to support both Rev0 and Rev 1.x boards. They might not be the best from a power PoV but they work just fine and it's a bit of a waste not to allow those who have some to use it.
* Work with the Vivado flow
My last attempt at this yielded some 'logic loop' during synthesis ... no idea what was going on since my verilog isn't all that good (I'm a VHDL guy
Cheers,
Sylvain