Routing additional Zynq hard block I/O to PEC_FPGA

[9600]

There has been some discussion about whether the Zynq's 2nd I2C and Ethernet controllers should be routed to GPIO pins, and presumably this could also be done for the 2nd UART or SDIO, or CAN bus or SPI.

Wondering if some of these interfaces should be routed to GPIO in the default image, on the assumption that this would be useful to many, and those who wish to implement some custom interface will be building their own image anyway. If so, what would be the ideal combination given the available pins?

Cheers,

Andrew

[parapara]

[FHuettig]

[9600]

[FHuettig]

[timpart]

A while back I commented that the UART has . I think I've since read somewhere in the Zynq`manual that GPIO lines can be used to provide RTS, CTS etc. So perhaps that could be an option too. Andrew @9600 had some cunning ideas for using a serial link I recall. (see the thread referenced above).

The control lines would be raw signals without a buffer chip like Tx and Rx have on the board, so some care might be needed.

I like the sound of Fred's I2C idea.

Tim

[rec]

In systems which consist of a single parallella board the PEC_NORTH and PEC_SOUTH signals could be looped back to each other inside the FPGA to form a ring with a single Epiphany chip in it. Or the elink lines could be just terminated with no connection inside the FPGA. Then the IOs on the PEC_NORTH and PEC_SOUTH connectors could be rerouted for other purposes.

-- rec --

[FHuettig]

[9600]

[parapara]