by siamon » Tue Jul 30, 2013 7:29 am
However one of the key features I would like to make here, is that unlike the ports on the Power Pec which are designed to inteface with the Zynq/Arm peripherals, the intention for Ziports here is to integrate directly into the epiphany cores. By that I mean the data/information flowing too and from Ziports should have the lowest possible latency (and the widest bandwidth) to the epiphany cores as is possible with the current design. This isn't totally direct of course as it is traversing through the Zynq's PL and then the epiphany HDL implementation (also insides the Zynq's gate fabric) but it is the closest we can get with what we have here.
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