PL fabric clock

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

PL fabric clock

Postby a_k » Wed Feb 17, 2016 9:52 am

Hi

I'm having some trouble getting the PL clocks to work (e.g. FCLK_CLK1). All I want is to route it to an I/O pin to use it with external hardware. I got a similar design running on a zedboard just fine, but I read that it is different on a Parallella. Apparently, the PL fabric clock configuration (FCLK_CLK0..3) is made in the PS. I saw people saying this gets configured in the FSBL, but on the Parallella, I don't have access to the FSBL because the operating system is loaded directly by the on-board u-boot bootloader and not the custom FSBL on the SD card. If this all is correct, I would have to change the clocks from the PS, but how do I do that? I don't think there can be much wrong with my design, as I am basically just routing a signal to an I/O and the other signals I have routed to an I/O are working fine. Or is there an additional step I might have missed?

Thanks
Last edited by a_k on Wed Feb 24, 2016 10:13 am, edited 1 time in total.
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Re: PL fabric clock

Postby peteasa » Fri Feb 19, 2016 4:24 pm

If you just change the clock speed in Vivado and rebuild the fpga then the bit stream created is not changed. When you use Vivado and create a new board support package the clock speeds selected for the PL clocks are saved in the board support package software. So the board support package is the only piece that is changed when you only configure changes to FCLK PL clocks in Vivado. The shipping first stage boot loader uses the board support package that was created some time ago and this then uses this old board support package to configure the clocks and fpga at startup. It is not possible to change the clock speed on the fly after boot because this change in clock would cause problems with various bits of hardware.

To change the clock speed you have to build a new board support package and create a new fsbl and flash this to the parallella via jtag.

I2C is used to configure the voltage regulators. In the fsbl the I2C interface is used to set the GPIO pin voltages. If you change the fpga then you must ensure that the I2C interface used is not changed so that the fsbl can still configure the voltages correctly.

You might find this of use: http://parallellagram.org/parallella-fp ... sion-cards
You might also find this of use: viewtopic.php?f=51&t=3297

Peter.
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Re: PL fabric clock

Postby kirill » Sun Feb 21, 2016 1:33 am

There seems to be a way to change PL clocks from Linux. This kind of makes sense since you can swap out bitstream from Linux, and not all bitstreams have the same clocks.

http://www.wiki.xilinx.com/Controlling+FCLKs+in+Linux

The interface is present under sys when using headless version at least

Code: Select all
find /sys -name "fclk*"
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Re: PL fabric clock

Postby kirill » Sun Feb 21, 2016 5:50 am

Here is an example that sets FCLK1 to 120MHz

Code: Select all
set -e

c=fclk1
devcfg=$(find /sys/devices -name "*.devcfg" -type d)
echo $c | sudo tee $devcfg/fclk_export > /dev/null

clk=$devcfg/fclk/$c
echo 1 | sudo tee $clk/enable > /dev/null
echo "Rate.Before:" $(cat $clk/set_rate)
echo 120000000 | sudo tee $clk/set_rate > /dev/null
echo "Rate.After :" $(cat $clk/set_rate)

echo $c | sudo tee $devcfg/fclk_unexport > /dev/null
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Re: PL fabric clock

Postby a_k » Wed Feb 24, 2016 8:40 am

Ok, thank you, that seems to be promising, but somehow I can't find those files.

Code: Select all
zynq> find /sys -name "fclk*"
/sys/devices/amba.2/f8007000.devcfg/fclk_unexport
/sys/devices/amba.2/f8007000.devcfg/fclk_export
/sys/class/fclk
zynq> ls -a /sys/class/fclk/
.   ..
zynq>


I'm using the kernel from the parallella git repository. Is this interface not included properly in this version?
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Re: PL fabric clock

Postby kirill » Wed Feb 24, 2016 10:06 am

But you do have them, it's just xdevcfg driver requires 3 step procedure:

1. echo fclk0 into /sys/{whatever_path_on_your_system}/fclk_export (Only then /sys/class/fclk/fclk0/* will appear)
2. Then enable it by echo 1 into /sys/class/fclk/fclk0/enable
3. Then change frequency by echo {needed_frequency_in_Hz} into /sys/class/fclk/fclk0/set_rate

Repeat for other clocks as needed by changing fclk0 to fclk{1,2,3}
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Re: PL fabric clock

Postby a_k » Wed Feb 24, 2016 10:41 am

Ah, ok, now I see. I thought you first have to change the parameters and then export them to apply the changes. Thank you! It works like a charm now!
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Re: PL fabric clock

Postby kirill » Wed Mar 16, 2016 10:47 am

For future references here is a script for changing fabric clocks from Linux

https://gist.github.com/Kirill888/24385a36697959924d78


Or for direct download:

https://gist.github.com/Kirill888/24385 ... a/fclk_set
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Re: PL fabric clock

Postby MelHance » Sat Aug 05, 2017 4:43 pm

a_ke wrote:Ah, ok, now I see. I thought you first have to change the legal steroids parameters and then export them to apply the changes. Thank you! It works like a charm now!


That was extremely helpful, thanks for the script kirill.
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