Attached is a sample project, demonstrating two methods provided by the eSDK for writing and using interrupt handlers.
A few notes:
The Epiphany's IVT is a table of relative branch instructions (not the target addresses!), with an entry for each event type. When an event occurs, the processor jumps to the respective entry (updating the return address to the IRET register) and performs whatever instruction it finds there. Normally, the branch will target the interrupt handler, which should be terminated by an RTI instruction. When programming an ISR in C, one uses the "interrupt" function attribute, so the compiler generates the appropriate interrupt handler code (like massive registers save and restore, and RTI instead of RTS).
Thus, the 1st entry is populated by the environment with a jump to the beginning of the program. Obviously, the entries cannot contain more than one 32-bit instruction.
Now, there are basically two ways of programming and registering an ISR - the direct and the indirect. With the direct method, one programs the ISR and then sets the branch address in the respective IVT entry to that ISR entry point. Currently, this needs to be done explicitly using pointers and constructing the opcode for the instruction.
Additionally, there's the indirect method. The C runtime provides a default interrupt dispatcher. This dispatcher handles all event types except for the lower two, and uses a function address table to invoke the actual user ISR. Here, the ISR should be registered using the signal() function call. Because the handling is done indirectly, this is a slower method (mostly negligible, though), but it is easier to implement.
The attached code shows the usage of the TIMER0 interrupt event. It is comprised of a host program which loads a master and a slave programs on cores 0x808 and 0x809 resp. After loading, the master is started, registering the ISR in one of the two methods (selectable at compile time with a macro definition), and starting the TIMER0 count. Once the counter reaches zero, the ISR is fired.
In the master's ISR, a "wake-up" signal is raised at the slave core. A mailbox in the DRAM is updated by the cores according to the program's advance, and is sampled by the host to show the program status.
** While writing this demo, I noticed that there is a discrepancy in the E-LIB, where some functions were programmed expecting to get different signal numbers than the default numbers of the E-LIB. There is an offset of 3 between the two sets of enumerations, so you can see the compensation in the master program, in the form of the SOFF constant.