Example DMA design (Vivado 2015.4)

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Example DMA design (Vivado 2015.4)

Postby kirill » Sat Jan 30, 2016 7:40 am

I have written a tutorial on how to do DMA transfer in and out of PL (Vivado 2015.4)

https://github.com/Kirill888/parallella-fpga-dummy-io/tree/master/sample_dma

Repository linked above includes Python library and a test app that interfaces with AXI DMA via UIO driver.

While the design I used as an example is a simple loopback, MM2S is connected to S2MM via a FIFO buffer, the same approach can be used for connecting more advanced accelerators, just replace the FIFO with your IP block.
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Re: Example DMA design (Vivado 2015.4)

Postby aolofsson » Sat Jan 30, 2016 2:48 pm

Awesome stuff! Thanks for doing this. I can't speak for others, but I learned something!
Andreas
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Re: Example DMA design (Vivado 2015.4)

Postby qrios » Sat Jan 30, 2016 10:02 pm

Hi kirill,

if you use your board on contained conditions you can ignore all fears about user rights. Given this, you can limit the kernel to a amount of memory. You only need to set the bootargs in the device tree to the upper limit of memsize (mem=512M -> 0x2000 0000). Beyond this, your program can mmap (read and write) without any hesitate.

Code: Select all
                bootargs = "root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait mem=512M isolcpus=1";


After this, you won't destroy your system (closed connection or even damage your rootfs - like me).

With the Direct Register Mode (you use) I was able to transfer up to 80MByte/s without any problems. The interesting point is the VHDL part. Currently I'm working directly in the IP-generated code.

Checking your github submits 2 times a day.
Just kidding. :)
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Re: Example DMA design (Vivado 2015.4)

Postby kirill » Fri Feb 05, 2016 10:17 am

Thanks for thumbs up Andreas. As someone from software background, who just recently started looking into all this FPGA stuff, I found relative sparsity of beginner friendly information online surprising. There is some good stuff out there no doubt, and I learned a lot from what's available, but for every FPGA "how to" there are hundreds "yet another Monad tutorials", and thousands of blogs on more mainstream topics. So I thought it's worth writing down my own investigations to help with that situation, and also few things give you more reason to gain that extra little bit of understanding than the fear of being wrong on the Internet.

@qrios

In this case 32Mb of already reserved memory is plenty enough, so I decided against making changes to that. But if you need more ram for your accelerator, doing what qrios suggests is probably the easiest way to reserve chunk of memory, just add mem=512M to bootargs section of the device tree and you have divided memory in two - one half for Linux one half for your accelerator/app.
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Re: Example DMA design (Vivado 2015.4)

Postby peteasa » Fri Feb 05, 2016 8:19 pm

There is also a user side helper library that may be of use that I have proven with the old version of the fpga see https://github.com/peteasa/examples/tre ... l/xdma_lib based on https://github.com/bmartini/zynq-xdma
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Re: Example DMA design (Vivado 2015.4)

Postby kwe » Fri Apr 29, 2016 11:31 am

Hi all! First post, just starting out.

Thanks for your sample projects, Kirill. I had problems using the UIO driver with the pre-compiled stock kernel and I guess people would want to compile it on their own at some point. I just wanted to bring up a few things I noticed for other newbies starting out as well:

I've successfully cross-compiled the newer kernel (4.4) with GCC 5 and gnueabihf on Ubuntu 15. Before that I used an older Git branch by mistake :roll: and the build errored out, so make sure to have the right sources & toolchains. (uboot tools as well)

I followed Kirills tutorial for the most part and the UIO drivers did only load after I compiled them into the kernel. (Not sure why, that may have been my mistake.) So menuconfig that and make sure they load.

Next thing is the /dev/<uio0> device didn't show up. This, I think, is due to some change in the kernel: https://github.com/Xilinx/linux-xlnx/commit/7ebd62dbc727ef343b07c01c852a15fc4d9cc9e5, also have a read: https://forums.xilinx.com/t5/Embedded-Linux/generic-UIO-broken/m-p/649759/highlight/true#M13903.

So if you follow Kirill's instructions you need to make changes to the devicetree.dts file you exported before and add some boot options uio_pdrv_genirq.of_id=generic-uio, i.e.:
Code: Select all
bootargs = "console=ttyPS0,115200 earlyprintk uio_pdrv_genirq.of_id=generic-uio root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";



That's it for now: devices showing up, kernel runs fine, looking forward to use that FPGA stuff. Sorry if this has already been discussed / pointed out somewhere obvious, I was too lazy to find that info.
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Re: Example DMA design (Vivado 2015.4)

Postby kirill » Tue May 03, 2016 12:50 pm

I finally had time to look at the new release.

I have been able to compile UIO driver for the stock 4.4 kernel, load and use it, however that kernel is missing Xilinx device configuration driver. So one can not easily reload fpga bitstream via /dev/xdevcfg, nor can you change FPGA clock frequencies without that driver. It is still possible to change fpga bitstream via /boot/parallella.bit.bin, and one can use uio driver as @qwe describes, but this requires reboot for every new bitstream test, and fixed clock configuration.

So I tried this linux kernel version:

https://github.com/Xilinx/linux-xlnx/re ... nx-v2016.1

It worked just fine for my needs. I haven't incorporated epiphany driver into it yet, but I do not expect that to be problematic.
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Re: Example DMA design (Vivado 2015.4)

Postby kirill » Sat May 07, 2016 12:26 pm

For those wanting to experiment with newer Kernel I recommend compiling your own version with UIO and xdevcfg. I made a patch and a script available here

https://github.com/Kirill888/parallella ... ter/kernel
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Re: Example DMA design (Vivado 2015.4)

Postby derekmulcahy » Sat May 07, 2016 2:30 pm

Thanks, very useful build.sh file. I have been struggling with the kernel build process.

On Ubuntu I had to install u-boot-tools to get the mkimage command.
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Re: Example DMA design (Vivado 2015.4)

Postby miguel_rodrigues » Mon May 16, 2016 11:24 am

Hi there :)

I learned a lot from this example even though at the time I didn't have a Parallella board, just a Zybo. Now, I am migrating all my FPGA designs using the Zybo to the Parallella.

One thing I noticed in this process is that using "mem=256M" in bootargs does not work, the board does not boot. At the same time, using "mem=512M" works fine.

I suspect that this arises from the configurations made in u-boot. In https://github.com/parallella/parallell ... q_common.h (lines 191 and 192) the addresses go to 0x20000000, which is equivalent to 512M. Hence, I assume that in order to be able to use mem=X in bootargs, one would need to change this addresses accordingly when X < 512M.

Is this assumption correct? Is there any step-by-step guide in order to compile u-boot, create the FSBL and so on until booting Linux on Parallella?

Kind regards :D
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