First step with parallella

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

First step with parallella

Postby zodane » Fri Feb 13, 2015 10:56 am

Hi,
I've just get my Parallella embedded platform. :D

But i have many issues.
I had never use ISE or Vivado, just some work with Modelsim.
also i'm new with zynq
:( :( :( :( :( :( :( :( :(

So i start with the architecture of the zynq, then i've took a look in forum and in parallellagram (by the way, i give thanks to Yani Dubin). But i can't find a way to program the parallella (there is many new terms Github, Planahead,...)

If i should understand and get familiarized with ISE, isn't better to do that with Vivado!!
Could any one share a tutorial of using Vivado with Parallella?
If i use Vivado should i do that only with a JTAG?
If i use Vivado can i still able to program the epiphany, and use HDMI,... ?

Could the Parallella board work without an OS (ARM Programmed as a Microcontroller??)
Is there a version of RTOS that can run in Parallella?
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Re: First step with parallella

Postby 9600 » Fri Feb 13, 2015 11:20 am

zodane wrote:Hi,
I've just get my Parallella embedded platform. :D

But i have many issues.
I had never use ISE or Vivado, just some work with Modelsim.
also i'm new with zynq
:( :( :( :( :( :( :( :( :(

So i start with the architecture of the zynq, then i've took a look in forum and in parallellagram (by the way, i give thanks to Yani Dubin). But i can't find a way to program the parallella (there is many new terms Github, Planahead,...)

If i should understand and get familiarized with ISE, isn't better to do that with Vivado!!
Could any one share a tutorial of using Vivado with Parallella?
If i use Vivado should i do that only with a JTAG?
If i use Vivado can i still able to program the epiphany, and use HDMI,... ?


So many questions! Sounds like you probably don't want to be messing around with the FPGA and ISE/Vivado, and instead simply use the Epiphany SDK. That is, unless you're experienced in FPGA development and this is what you're particularly interested in.

Could the Parallella board work without an OS (ARM Programmed as a Microcontroller??)


Yes, this is possible, but I imagine some work would then be required in order to still access the Epiphany.

Is there a version of RTOS that can run in Parallella?


Yes, patc has a project which uses FreeRTOS, and there may be others.
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Re: First step with parallella

Postby zodane » Fri Feb 13, 2015 2:34 pm

Thank you Andrew for replying (to some questions ;) )

I bought the Parallella for a big project, the porcupine wasn't available so i bought the connectors too. :)

- This is the first Parallella in my country (as i know) and if i can manage it to work with an pedagogical way it will be studied in my university

- I want to implement the results of my research (video processing) in the Parallella and write some paper about that, i just need to know how to start. So there is some co-design (epiphany+PS+PL) and all should work in a real time.

9600 wrote:
So many questions! Sounds like you probably don't want to be messing around with the FPGA and ISE/Vivado, and instead simply use the Epiphany SDK. That is, unless you're experienced in FPGA development and this is what you're particularly interested in.


Actually this is not an option, so i have to work with one of them ISE or Vivado; and i prefer to work with Vivado is it that possible (only with Jtag?) can i still work with epiphany if i do so?

Regards
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Re: First step with parallella

Postby 9600 » Fri Feb 13, 2015 3:02 pm

zodane wrote:This is the first Parallella in my country (as i know) and if i can manage it to work with an pedagogical way it will be studied in my university


Interesting. Can I ask where you are located? Just curious!

I want to implement the results of my research (video processing) in the Parallella and write some paper about that, i just need to know how to start. So there is some co-design (epiphany+PS+PL) and all should work in a real time.


Right, so you do need to use the Xilinx tools. Wasn't sure at first if you had a simpler idea in mind that just required use of the eSDK.

Actually this is not an option, so i have to work with one of them ISE or Vivado; and i prefer to work with Vivado is it that possible (only with Jtag?) can i still work with epiphany if i do so?


The FPGA bitstream file lives on the BOOT volume of the Micro SD card and so you don't need to use JTAG to reconfigure this. If you want to still be able to use the Epiphany and/or HDMI, you will obviously need to extend one of the the existing projects. My understanding is that there remains some work still to be done before there is a fully functional flow for Vivado, although I could be wrong. ISE is certainly the more trodden path at this point in any case.

Look forward to hearing about your progress!

Regards,

Andrew
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Re: First step with parallella

Postby zodane » Fri Feb 13, 2015 6:10 pm

The FPGA bitstream file lives on the BOOT volume of the Micro SD card and so you don't need to use JTAG to reconfigure this.

and what make the board Boot from SD card?
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Re: First step with parallella

Postby patc » Sat Feb 14, 2015 10:33 pm

just my 2 cents:

If i should understand and get familiarized with ISE, isn't better to do that with Vivado!!

If you're willing to use the Zynq in standalone from scratch and at your own risk you can use Vivado. Else you have to wait for Adapteva to complete the move to Vivado

Could any one share a tutorial of using Vivado with Parallella?

http://svenand.blogdrive.com/archive/16 ... N_EQU10xlY
but again, Zynq in standalone from scratch, no Epiphany. Check one of my previous posts for DDR settings. However you should also be aware that in such case the ISL9305 will default to 1.5V to SDRAM instead of 1.35V

If i use Vivado should i do that only with a JTAG?

yes

If i use Vivado can i still able to program the epiphany, and use HDMI,... ?

see previous

Could the Parallella board work without an OS (ARM Programmed as a Microcontroller??)

Absolutely, standard Cortex A9 stuff

Is there a version of RTOS that can run in Parallella?

As Andrew said, I'm using FreeRTOS and so far it seems to be working fine.

and what make the board Boot from SD card?

FSBL in QSPI flash
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Re: First step with parallella

Postby 9600 » Sun Feb 15, 2015 11:12 am

FSBL in QSPI flash


And U-boot also.

Regards,

Andrew
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Re: First step with parallella

Postby zodane » Mon Feb 16, 2015 7:30 am

Patc and Andrew thank you for clarification

Regards
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Re: First step with parallella

Postby zodane » Wed Feb 18, 2015 12:06 pm

Hi,
Now i'm starting with programmation the ARM cores using Xilinx SDK. :? :?
i have some issues
1- What should i select in Hardware platform (Xilinx SDK)
1.jpg
1.jpg (163.32 KiB) Viewed 17465 times

2- Once i have generate the program (supposed to run in ARM) how can i move it to parallella (UART, µSD,... ?)

Regards
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Re: First step with parallella

Postby patc » Wed Feb 18, 2015 1:34 pm

I assume you're using Vivado and want to try the Hello_World example. May be you can try out the following:

- Make a Vivado project for your Parallella with the bare minimum (just UART1 MIO 8..9). Then generate the bitstream. You are NOT going to download the bitstream to the FPGA but you need the correct hardware platform to get SDK to generate the proper BSP (I'm using my own bistream but I assume this procedure should work as well with the Adapteva bistream as it is)

- switch to SDK
- New-Project-Hardware Platform Specification -> select previously created bitstream
- New-Application Project -> test with ps7_cortexa9_0, standalone and create new test_bsp
- select Hello World
- build test
- Run-Debug Configuration and New Xilinx C/C++ application (GDB)
- uncheck "Run ps7_init" and "Run ps7_post_config"

should be like the following:

Following operations will be performed before launching the debugger.
1. Reset processor.
2. 'C:\Users\pat\workspace2014_3_7020\test\Debug\test.elf' will be downloaded to the processor 'ps7_cortexa9_0'

- connect a terminal to your Parallella serial port (115200 bauds)

- then run it (JTAG to download to the Parallella)
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