Developing an FPGA sandbox

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Re: Developing an FPGA sandbox

Postby cmcconnell » Thu Oct 16, 2014 1:06 am

Hi Andreas,

Thanks for responding.

aolofsson wrote:Vivado is not hard to use, the lengthy transition time has to do with limited resources. (progress is being made...and there will be a delivery soon...sorry no date..)

If you want to play around with FPGA design using Vivado, you certainly don't need Adapteva and I would recommend moving ahead independently.


Do you mean move ahead on the Parallella, or are you suggesting I start with an alternative FPGA dev board? (I'd be very wary of doing anything on the Parallella without some kind of template from which to start, for fear of causing damage. I suppose the ideal scenario would be for the Parallella to appear alongside the Zedboard, etc. in the list of selectable targets.)

In case there's any confusion, I don't have any particular attachment to Vivado, and I'm not in any great hurry to get started. But at some point in the not-too-distant future I would like to play around with FPGA design using the Parallella (with the ultimate goal of developing heterogeneous applications, making simultaneous use of ARM, FPGA, and Epiphany) .

I wouldn't want to start off using ISE if the transition to Vivado is just, say, six weeks away. On the other hand, if it's more like six months, I doubt I'll be able to resist the temptation to dive in before then.

Also, I think the majority of the Zynq tutorials I've so far come across assume Vivado, so I suppose that is another motivating factor.

I raised the query with regard to the work Yani is doing for similar reasons, wondering if he was going to be overtaken by events. For instance, I don't really know anything about FuseSoc, or how it works with ISE, but I gather Vivado has extensive command-line support via tcl scripts, which sounds like it plays the same role.
Colin.
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Re: Developing an FPGA sandbox

Postby aolofsson » Thu Oct 16, 2014 3:35 am

Colin,

There is VERY little risk in actually damaging the board using the Vivado FPGA tools. I am sure Fred can give a pointer to an "empty" Vivado projects with just pin constraints to get it going.

The project containing a true heterogeneous platform is with everything working perfectly together in Vivado is still in progress.

Andreas
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Re: Developing an FPGA sandbox

Postby Len » Fri Nov 07, 2014 5:45 pm

I am eager to start working with the FPGA and was hoping to work with Vivado. Can you give any status as to how the port is coming?
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Re: Developing an FPGA sandbox

Postby FHuettig » Fri Nov 07, 2014 6:05 pm

Hi Len,

I'm very actively working on this and should have the first release out any day now.

-Fred
-- Fred -- Hardware Guy --
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Re: Developing an FPGA sandbox

Postby fuzz » Sun Nov 09, 2014 8:40 pm

FHuettig wrote:Hi Len,

I'm very actively working on this and should have the first release out any day now.

-Fred


I'm installing Vivado in a VM right now, also eager to start playing with this :)
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Re: Developing an FPGA sandbox

Postby mikebell » Wed Jan 14, 2015 10:38 pm

I just downloaded Vivado before reading that the Parallella project still uses ISE - did that sample "empty" Vivado project ever get created?

It would be nice to have a starting point to work from and try a few things out even if I can't use the Epiphany with custom designs quite yet.
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Re: Developing an FPGA sandbox

Postby peteasa » Wed Sep 09, 2015 3:51 pm

I did a quick search of "Vivado simulator" in the forum and this is the only thread that looked appropriate to point to my elink2 fpga simulator tutorial and script (https://github.com/peteasa/parallella/w ... Simulation) that I have just created that uses my parallella development project. My parallella development project provides a good starting point for FPGA / software development for the parallella board. At present I am only using the elink2 fpga, but plan to move to use the oh fpga projects in the future.

The most important thing for any fpga sandbox would be to ensure that the i2c interface is operational as this is used in the boot loader to configure the regulators. An alternative of course would be to develop your own boot loader.. but then thats another thing to go wrong and so the FPGA sandbox should I think not require an updated boot loader.

I will be interested to see over time how easy it is to track different versions of Vivado simulator!
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