$2.5K and $10K Prototype Boards

[mrgs]

Hi All, As I guessed I have 'something' on my test Zed by end of this week. --- Attached please find a screen-shoot ---. Well, it was not so easy as I like. But finally I have: - 'Complex?!' Xilinx ISE environment on a GNU/Linux host, - Working 'GUI based' GNU/Linux system on Zed, compose by myself from source (u-boot, Linux kernel) + Linaro FS from Linaro. My suggestion: Please use 'Linaro-Alip' rather than 'Linaro-Ubuntu-Desktop' "File System". As You see?! this is a XGA resolution screen via VGA connector. I am going to switch to HDMI. So, I have to use a different Programmable Logic (PL) project (credit for ADI). --- It (monitor handling) was a surprise?! for me ---. But at 'least' I will ready to a totally hack both PL and PS side too(!) Oh... tons to learn before the BIG GAME with Parallella. Regards, Gabor

[aolofsson]

Wow, that was fast! I am seriously impressed. You showed again why we need to hurry up and release all of the sources.
Andreas

[mrgs]

To Andreas: My pleasure to prepare a little technical stuff and myself for Your CPU mesh. At the 'end of the story' I would like to say: "Zed's dead, baby. Zed's dead." ... I will get home as Parallella board spin up with "my" little OS. Take it easy, time does not matter. It is just a pure illusion.

Back to the relative World : Well, my next steps: - Zynq programmable logic hack (let me see how does it work ... Oops another language ( VHDL?!) I have to 'fall in love again' ) - More speed from processing system via hard-float. ( CROSS_COMPILE=arm-linux-gnueabihf- )... Wow : PS + PL + CPU mesh + OS(s). Is this the 'heaven' OR 'hell'? It is up to You. Regards, Gabor

[ysapir]

@mrgs,

"Time not important. Only life important"

[ed2k]

[ubii]

mrgs,

Just curious, is the output that you posted on the 23rd from the same ZedBoard as what you posted on the 27th? The reason why I ask, is that I noticed that the Xilinx image from the 23rd has 1594.16 BogoMIPS listed in /proc/cpuinfo, while the Linaro-Alip image from the 27th has 1332.01 BogoMIPS listed. My understanding is that the Zynq-7000 series CPUs come in three speed grades, which are listed below.

-1: 667 MHz
-2: 733 MHz
-3: 800 MHz

Based upon the BogoMIPS listed, I am assuming that the CPU is running at 800 MHz on the Xilinx image and 667 MHz on the Linaro-Alip image. Assuming that both of these images were running on the same Zedboard, I wonder if the XML board description file on the Xilinx image actually has the CPU speed grade set to -3, instead of -1? What is interesting, is that /proc/cpuinfo on my prototype board has 1332.01 BogoMIPS listed (meaning 667 MHz), but the output of the matmul-16 example lists it at 800 MHz.

EDIT: After reading through numerous posts on the ZedBoard forum (http://www.zedboard.org/forums/zedboard-english-forum), it appears that the current Zedboards are shipping with ES (Engineering Sample) grade silicon, meaning that they are supposedly limited to speed grade -1 (667 MHz). The production version of the ZedBoards is expected to ship sometime during the first half of 2013 and will support higher clock speeds. Hopefully, the production version of the Zynq chips will be available this May, for use on the initial batch of Parallella boards.

[mrgs]

[ubii]

mrgs,

Yes, I realize that BogoMIPS are really not a proper method of calculating CPU clock speed, but the fact that there was almost a 20 percent difference in the BogoMIPS listed between each image, is what got me curious. As I later found out after reading the ZedBoard forums, the current ZedBoards are only shipping with ES grade silicon, which is limited to 667 MHz.

The source of my confusion regarding the clock speed listed in the matmul-16 example, is the fact that the version of this example in the current SDK differs from the version on my prototype board. The current SDK version, which is what I had previously looked at, appears to calculate the clock speed for both the Epiphany and ARM chips while the version of that example on my prototype board actually defines the clock speed.

Current SDK - (excerpt from /opt/adapteva/esdk/examples/matmul-16/matmul-16_host/src/matmul_host.c)

#define eMHz 400e6

tdiff[0] = ((double) clocks) / eMHz * 1000;
tdiff[1] = (timer[3].tv_sec - timer[2].tv_sec) * 1000 + ((double) (timer[3].tv_usec - timer[2].tv_usec) / 1000.0);

fprintf(fo, "Epiphany - time: %9.1f msec (%u cycles)\n", tdiff[0], clocks);
fprintf(fo, "Host - time: %9.1f msec\n", tdiff[1]);

Prototype SDK - (excerpt from /opt/adapteva/esdk/examples/matmul-16/matmul-16_host/src/matmul_host.c)

#define eMHz 600
#define aMHz 800

fprintf(fo, "Epiphany - time: %9.1f msec (@ %03d MHz)\n", tdiff[0], eMHz);
fprintf(fo, "Host - time: %9.1f msec (@ %03d MHz)\n", tdiff[1], aMHz);

[ysapir]

@ubii,

I am not sure what is the "Current SDK" and "Prototype SDK". The latest eSDK that we released was v 4.13.01.04 . This is the latest version, intended for Parrallella Prototype system (ZedBoard + Epiphany). There, there the Epiphany speed is 600MHz and the ARM speed was #defined as 800MHz, but it should probably be 667MHz, as per the ZedBoard docs (the example code was developed on a different Zynq based board).

I guess that the 400MHz Epiphany speed example version that you have comes from the EMEK3 system release. This is the clock speed on that daughter card. In that version of the example, I used the Epiphany timers to measure the calculation time, because the host-device communication channel was horribly slow. On the Zynq based systems, the measurement uses the linux "wall clock" for measuring the total computation time (including host-device I/O).

[ubii]

ysapir,

Sorry, I should have been more specific regarding the the two SDK versions. The SDK that I "currently" have installed on my Linux system is the older 3.12.11.20 version, which was made available to us back in December. This is the one that I had originally looked at the matmul-16 source, which is why I was confused. The SDK version on my prototype board is in fact the newer 4.13.01.04 version. If I would have simply looked at the matmul-16 source on my prototype system, where I actually ran the program, I would have seen that the clock speed was defined for both the Epiphany and Arm chips.