Timing violation of Parallella PFGA project

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Timing violation of Parallella PFGA project

Postby jimmystone » Sun May 21, 2017 8:58 am

Hi, All

I am using the Oh!https://github.com/parallella/oh to compile a new FPGA of
headless_e16_z7020

And I notice there are some timing violation after PAR in Vivado.
Do these violations matter? Should I mask these path with false path?

Thanks.
jimmystone
 
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