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When using EMIO do I need to rebuild the FSBL

PostPosted: Thu Mar 30, 2017 1:31 pm
by wiegmink
Hi all,

Not sure if the questions belongs here, but is is closely related to HW design. I've added SPI0 in the MIO configuration, io is routed through EMIO to a component in the PL (and from there to the outside world). Xilinx issue 47511 taken into account. Question is if I use EMIO do I need to rebuild the FSBL? (Or maybe in general do I always need to rebuild the FSBL if the configuration is changed?)

Thanks.

Re: When using EMIO do I need to rebuild the FSBL

PostPosted: Fri Mar 31, 2017 12:01 pm
by wiegmink
In the mean time I've got output signals, so the answer is you don't need to rebuild the FSBL. (Apparently posting questions already helps.) :)
The only thing is that the speed option in the spidev_test.c doesn't do much. Output clock is pretty fixed at 645 kHz. Anyway, next thing to look at, this item is closed.

Re: When using EMIO do I need to rebuild the FSBL

PostPosted: Sat Apr 01, 2017 1:48 pm
by olajep
Check this thread out:
https://parallella.org/forums/viewtopic.php?f=48&t=4018

Does it help if you change spi-max-frequency in the device tree?
Code: Select all
...
  spi-max-frequency= <800000>;
...


Linux kernel spi devicetree bindings documentation:
https://www.kernel.org/doc/Documentatio ... pi-bus.txt

// Ola