Troubles rebuilding the FPGA

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Troubles rebuilding the FPGA

Postby avignani » Fri Sep 16, 2016 11:20 pm

Hello,
I bought a z7020 parallella in 2014, and successfully modified linux 3.14 and the ZYNQ for my application (e.g. adding CAN, LEDS etc.). All modifications were done with ISE 14.7 and worked with no troubles.

Now, last week I started upgrading the parallella to linux 4.4 and Vivado, but without success.
What I did was:
- get the latest SD image with ubuntu 15.04, install and run it. All went Ok, but of course my peripherals weren't there.
- recompile and reflash the u-boot from the ESDK 2016.3 (for running the UART at 921600). All Ok.
- replace the kernel and device tree with those from my 4.4.20 version. Still all Ok.
- download and install Vivado 2014.3 Webpack under linux (note that I use mageia 4, shouldn't matter).
- get the latest(?) FPGA from the parallella-hw archive and, not changing anything, rebuild with vivado 2014.3 following your instructions.
all went smoothly.. well, almost; see the warning below.
Put the bitfile on the SD card, restart and... the kernel hangs accessing the Epiphany (I know because it works if I remove the Epiphany driver, and also by comparing the logs).
To be sure I restored your kernel, and the system still hangs. So it's either the FPGA sources, or Vivado, or Vivado under linux.

Now for the critical warnings I got from Vivado 2014.3:
CRITICAL WARNING: [Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.
CRITICAL WARNING: [Memdata 28-148] Could not complete initialization of processor data. Could not create the file: /usr/local/parallella/parallella_7020_headless/parallella_7020_headless_gpiose_elink2.runs/impl_1/elink2_top_wrapper.mmi

There was another warning about a mismatch in MASTER_TYPE between BRAM and axi_ctrl, or something similar, but I can't find it in the logs.

Questions:
how did you generate the FPGA bitfile on the official SD? Are these sources available? And where?
could these warnings be the cause of the missing Epiphany interface? Are they linux-specific? And how to correct them?
BTW, why some of the epiphany tests in your SD card under /home/parallella fail to build, or fail to execute?

-------
Update: Vivado 2014.3.1 under Windows gives exactly the same warnings and produces the exactly same bitfile, which of course doesn't work.
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Re: Troubles rebuilding the FPGA

Postby peteasa » Mon Sep 19, 2016 5:31 am

FPGA project source: https://github.com/parallella/oh
Official release of bitstream (no hdmi): https://github.com/parallella/pubuntu/t ... a_bitfiles
Look on this forum for assistance on the bmm_info warnings that are not critical.

Peter.
PS. My unofficial environment where it all works including hdmi: https://github.com/peteasa/parallella/wiki
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Re: Troubles rebuilding the FPGA

Postby avignani » Mon Sep 19, 2016 7:19 pm

Thank you!
With your instructions I was able to rebuild a bitfile that works, or at least behaves like the official one. (I have still to look into the 2016.3 ESDK tests and see why some of them fail, but it's a big step ahead anyway).

Alberto
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Re: Troubles rebuilding the FPGA

Postby frankbuss » Mon Aug 07, 2017 11:54 pm

I installed Vivado 2017.2 and tried to build the standard FPGA bitstream which is included in the Parabuntu distribution. I have an A101040 board and would like to build the headless version. The Parabuntu release for this board works on my system.

I used the repository https://github.com/parallella/oh. Then I guess I have to go to src/parallella/fpga and run "make", after setting the environment with "setenv.sh"? I tried this and get lots of errors, warnings and critical warnings. Here is the full output:

https://pastebin.com/APXqJ36A

Is there a tutorial how to compile the bitstream? Is this even possible with the new Vivado version? Looks like some error messages say it was created with an earlier version. Anyone who managed to compile it with Vivado 2017.2 and could save it somewhere on github, or maybe the original "oh" repository could be updated?
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Re: Troubles rebuilding the FPGA

Postby olajep » Wed Aug 09, 2017 1:57 pm

frankbuss wrote:I installed Vivado 2017.2 and tried to build the standard FPGA bitstream which is included in the Parabuntu distribution. I have an A101040 board and would like to build the headless version. The Parabuntu release for this board works on my system.

I used the repository https://github.com/parallella/oh. Then I guess I have to go to src/parallella/fpga and run "make", after setting the environment with "setenv.sh"? I tried this and get lots of errors, warnings and critical warnings. Here is the full output:

https://pastebin.com/APXqJ36A

Is there a tutorial how to compile the bitstream? Is this even possible with the new Vivado version? Looks like some error messages say it was created with an earlier version. Anyone who managed to compile it with Vivado 2017.2 and could save it somewhere on github, or maybe the original "oh" repository could be updated?


1. You need to have Vivado 2015.2 and SDK 2015.2 installed
2. Use the "stable" branch of oh

From scratch:
Code: Select all
source /opt/Xilinx/Vivado/2015.2/settings64.sh
source /opt/Xilinx/SDK/2015.2/settings64.sh
git clone https://github.com/parallella/oh
cd oh
git checkout stable
cd parallella/fpga
make

That will build the parallella ip and the z7010 and z7020 bitstreams we use in the headless Parabuntu images.

HTH,
Ola
_start = 266470723;
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Re: Troubles rebuilding the FPGA

Postby frankbuss » Wed Aug 09, 2017 4:36 pm

Thanks, I tried it. Running "xsetup" said "ERROR: This installation is not supported on 32 bit platforms". But this was just a wrong test with "uname", I could just comment this in the xsetup file, which is a bash script (I'm using 64 bit Debian Linux, there was not such a problem with the Vivado 2017.2 version). And looks like the 2017 version didn't need all the manual work to get and install a licence for the WebPACK version. I found the bitstream in "headless_e16_z7020/parallella_e16_headless_gpiose_7020.bit.bin" after your steps, and it works.

But I noticed this when compiling: "43 Infos, 102 Warnings, 100 Critical Warnings and 0 Errors encountered.". In my FPGA designs I always try to reduce this to 0 warnings, which is not always possible, but 100 critical warnings is a lot. Most of them looks easy to solve, like some unknown property name. The advantage of having only a handful of warnings is that you don't miss the important ones ;)

Any plans to port it to Vivado 2017.2?
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