[phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead
[phpBB Debug] PHP Warning: in file [ROOT]/includes/functions.php on line 4688: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823)
[phpBB Debug] PHP Warning: in file [ROOT]/includes/functions.php on line 4690: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823)
[phpBB Debug] PHP Warning: in file [ROOT]/includes/functions.php on line 4691: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823)
[phpBB Debug] PHP Warning: in file [ROOT]/includes/functions.php on line 4692: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823)
Parallella Community • View topic - How about computing a cosine in FPGA
Page 1 of 1

How about computing a cosine in FPGA

PostPosted: Tue Jun 14, 2016 2:30 pm
by theover

Re: How about computing a cosine in FPGA

PostPosted: Wed Jun 15, 2016 10:27 pm
by theover
Today I tried making a (double) cos((double) angle) to fit in the Zynq FPGA, and at the expense of about half the LUTs, it fits, and (with similar program) appears to work to the accuracy of e-16 compared with Arm double precision math. It does about CD audio rate of computing double cosine values, but I read there are pragmas to do pipelining.

T.V.

Re: How about computing a cosine in FPGA

PostPosted: Tue Jun 21, 2016 2:38 pm
by theover
I've spent a few days studying the vivado_hls tutorial in :

ug871-vivado-high-level-synthesis-tutorial.pdf

and part of the manual in:

ug902-vivado-high-level-synthesis.pdf

And after trying some of the examples and having loaded a few examples in the existing Parallella project referenced above, it is safe to say there is serious potential in Vivado2016.1 + Vivado_HLS to get a C function to act as a piece of FPGA code that can also be connected up to the AXI (in my case "lite") bus to communicate with the Zynq's ARM cores.

The Tcl interpreter in Vivado can be extended with external code, the IP library is considerable and contains powerful blocks (like FFT, Cordic, memory constructs, etc. etc that in this version mostly are free to use for Webpack users ! That's a big thumbs up for Xilinx! The RTL simulator also works both in _hlx and the main vivado (though I don't know if it is possible to connect with the "logical analyze" block that is available from the IP lib), and the C code cross check compilation and C versus hardware compiled C compilation and simulation works smooth and efficient.

So after doing some of the tutorial examples in practice I want to try if, with the right directives, a C function can also be used to do user IO and connections with self-made IP blocks.

Anyhow, it's recommended for those into the Zynq as fast(-er) turnaround prototype machine.

T.

Re: How about computing a cosine in FPGA

PostPosted: Tue Aug 09, 2016 3:52 pm
by NeilKeiding
Hi...i am new here. I want yo ask you something about this "And after trying some of the examples and having loaded a few examples in the existing Parallella project referenced above, it is safe to say there is serious potential in Vivado2016.1 + Vivado_HLS to get a C function to act as a piece of FPGA code that can also be connected up to the AXI (in my case "lite") bus to communicate with the Zynq's ARM cores." Can you please tell me what examples did you used?