Vivado HLx 2016.1 C to FPGA

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Vivado HLx 2016.1 C to FPGA

Postby theover » Thu May 19, 2016 8:59 pm

Hi all,

I've, a while ago, looked at including silicon compilation from C code to bit file with Linux driving, with (limited) success, see here:
http://forums.parallella.org/viewtopic.php?f=51&t=3376&hilit=HLx "Xilinx Webpack 2015.4 HLx edition".

Now the other day I downloaded the latest (no licence!) Webpack Vivado on my fast machine (it includes an amount of multi threading and caching of intermediate results it seems), tried to upgrade some test project I had, which worked without checking the bitfile, and looked at some more C examples, hoping for a better way to automatically create the AXI interface from the results of vivado_hl and maybe finding it could create some Linux side C driver programs.

Now, the examples on the design computer run fine, the C code versus VHDL simulator results works and matches, and maybe there are more examples this time (I don't recall) like streaming and some matrix examples. But, Apart from my own solution I mentioned in the thread I quoted above, there's certainly not an automated path I can find that lets the FPGA talk with a C program on the Zynq ARM in an easy way.

Does anybody know more about this?

T>
theover
 
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Re: Vivado HLx 2016.1 C to FPGA

Postby kirill » Thu May 19, 2016 10:08 pm

Hi Theo,

The Xilinx tool that is supposed to "automagically, but with human guidance, partition computation between CPU and FPGA" is called SDSoC

http://www.xilinx.com/products/design-t ... sdsoc.html

From what I understand it uses HLS to compile code to gates, but also adds integration layer that deals with drivers, and physical memory, and AXI streams, and DMA, and building a bitfile. I haven't actually used it enough to make a judgement on how well it manages. I suspect that if you really need last bit of performance this might not be the tool, but it certainly helps if all you want is a quick prototype and a convenient dev environment.

Now, it's not free, nor cheap. And getting it to work with unsupported board like Parallella might be tricky.
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Re: Vivado HLx 2016.1 C to FPGA

Postby theover » Wed May 25, 2016 1:53 pm

Right, that was cool, but indeed the SW costs about $1000,- and the hardware featured probably is the price of many Parallella boards.

it was interesting to see a video application consisting of a number of C functions acting on a live HDMI stream getting put into Zynq FPGA accelerated code automatically! The whole chain creates an SD card, which takes a while, which then can be booted. I'd like to have some more fine grained interaction options, and preferably partial reconfiguration, but I suppose after pro norms the software isn't that expensive for people that want it.

What I mean is though that I have mad ea connection with a simple AXI interface talking with a vivado_hl C to Verilog compiled function, but the HL examples include more complicated AXI communication like DMA, which I think should be connectable to a Linux C program, too!

T.
theover
 
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Re: Vivado HLx 2016.1 C to FPGA

Postby theover » Fri Sep 02, 2016 9:17 am

I've tried some examples with 16.1 and 16.2 _HLS, and it appears projects with HLS IP can be imported in the basic Zynq project with AXiLite interface.

I've yesterday tried only C-to_verilog with the main DSP update routine of an older project of mine ("string simulator" for musical use), which contains a number of update sweeps on integer data arrays and scaling operations, and hurray, it gets through the compiler, and can fir the 7010 ! So that will be a bit of work for me to try to get something practical from. When that works practically I'll wrap an example project up and put it on here.

T.
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