Example DMA design (Vivado 2015.4)

[kirill]

I have written a tutorial on how to do DMA transfer in and out of PL (Vivado 2015.4)



Repository linked above includes Python library and a test app that interfaces with AXI DMA via UIO driver.

While the design I used as an example is a simple loopback, MM2S is connected to S2MM via a FIFO buffer, the same approach can be used for connecting more advanced accelerators, just replace the FIFO with your IP block.

[aolofsson]

Awesome stuff! Thanks for doing this. I can't speak for others, but I learned something!
Andreas

[qrios]

[kirill]

Thanks for thumbs up Andreas. As someone from software background, who just recently started looking into all this FPGA stuff, I found relative sparsity of beginner friendly information online surprising. There is some good stuff out there no doubt, and I learned a lot from what's available, but for every FPGA "how to" there are hundreds "yet another Monad tutorials", and thousands of blogs on more mainstream topics. So I thought it's worth writing down my own investigations to help with that situation, and also few things give you more reason to gain that extra little bit of understanding than the fear of being wrong on the Internet.

@qrios

In this case 32Mb of already reserved memory is plenty enough, so I decided against making changes to that. But if you need more ram for your accelerator, doing what qrios suggests is probably the easiest way to reserve chunk of memory, just add mem=512M to bootargs section of the device tree and you have divided memory in two - one half for Linux one half for your accelerator/app.

[peteasa]

There is also a user side helper library that may be of use that I have proven with the old version of the fpga see https://github.com/peteasa/examples/tre ... l/xdma_lib based on https://github.com/bmartini/zynq-xdma

[kwe]

[kirill]

I finally had time to look at the new release.

I have been able to compile UIO driver for the stock 4.4 kernel, load and use it, however that kernel is missing Xilinx device configuration driver. So one can not easily reload fpga bitstream via /dev/xdevcfg, nor can you change FPGA clock frequencies without that driver. It is still possible to change fpga bitstream via /boot/parallella.bit.bin, and one can use uio driver as @qwe describes, but this requires reboot for every new bitstream test, and fixed clock configuration.

So I tried this linux kernel version:

https://github.com/Xilinx/linux-xlnx/re ... nx-v2016.1

It worked just fine for my needs. I haven't incorporated epiphany driver into it yet, but I do not expect that to be problematic.

[kirill]

For those wanting to experiment with newer Kernel I recommend compiling your own version with UIO and xdevcfg. I made a patch and a script available here

https://github.com/Kirill888/parallella ... ter/kernel

[derekmulcahy]

Thanks, very useful build.sh file. I have been struggling with the kernel build process.

On Ubuntu I had to install u-boot-tools to get the mkimage command.

[miguel_rodrigues]

Hi there

I learned a lot from this example even though at the time I didn't have a Parallella board, just a Zybo. Now, I am migrating all my FPGA designs using the Zybo to the Parallella.

One thing I noticed in this process is that using "mem=256M" in bootargs does not work, the board does not boot. At the same time, using "mem=512M" works fine.

I suspect that this arises from the configurations made in u-boot. In https://github.com/parallella/parallell ... q_common.h (lines 191 and 192) the addresses go to 0x20000000, which is equivalent to 512M. Hence, I assume that in order to be able to use mem=X in bootargs, one would need to change this addresses accordingly when X < 512M.

Is this assumption correct? Is there any step-by-step guide in order to compile u-boot, create the FSBL and so on until booting Linux on Parallella?

Kind regards